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Description
Bugzilla Link | 2827 |
Resolution | FIXED |
Resolved on | Nov 07, 2018 00:22 |
Version | 2.3 |
OS | All |
Reporter | LLVM Bugzilla Contributor |
Extended Description
In generated XXXCodeEmitter::getBinaryCodeForInstr(MachineInstr &MI) tablegen produce wrong values, if a 32 bit instruction operand is used. So the generated code looks like this:
case sharc::PUSHGAddr: {
// op: registerINumber
op = getMachineOpValue(MI, MI.getOperand(0));
Value |= (op & 7U) << 41;
// op: registerMNumber
op = getMachineOpValue(MI, MI.getOperand(1));
Value |= (op & 7U) << 38;
// op: immediateData
op = getMachineOpValue(MI, MI.getOperand(2));
Value |= op & 0U; // <<<<<<<<<<<<<<<<<<<<<<<<<<<< BUG.
break;
}
The reason for that is that in CodeGenEmitterGen.cpp line 190:
unsigned opMask = (1 << N) - 1;
If N=32, than the opMask is zero, instead of 0xffffffff
Solution:
CodeGenEmitterGen.cpp line 190:
unsigned opMask = (1ULL << N) - 1;