SIOptimizeVGPRLiveRange introduces register with broken liveness

[arsenm]

This testcase fails the verifier after SIOptimizeVGPRLiveRange runs:

Checking IF-ELSE-ENDIF: %bb.1 %bb.2 %bb.4
Found Else blocks: %bb.1 %bb.3 %bb.0 
Optimizing %4
Removing AliveBlock %bb.1
Clear AliveBlock %bb.4

# After SI Optimize VGPR LiveRange
# Machine code for function wobble: IsSSA, TracksLiveness

bb.0:
  successors: %bb.1(0x80000000); %bb.1(100.00%)

  %0:sreg_32 = S_ADD_U32 undef %1.sub0:sgpr_64, 32, implicit-def $scc
  %2:sreg_32 = S_ADDC_U32 undef %1.sub1:sgpr_64, 0, implicit-def dead $scc, implicit killed $scc
  dead %3:sreg_64 = REG_SEQUENCE killed %0:sreg_32, %subreg.sub0, killed %2:sreg_32, %subreg.sub1
  %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

bb.1:
; predecessors: %bb.0
  successors: %bb.2(0x40000000), %bb.4(0x40000000); %bb.2(50.00%), %bb.4(50.00%)

  %5:sreg_64 = V_CMP_LT_I32_e64 0, %10:vgpr_32, implicit $exec
  %6:sreg_64 = SI_IF killed %5:sreg_64, %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  S_BRANCH %bb.4

bb.2:
; predecessors: %bb.1
  successors: %bb.4(0x40000000), %bb.3(0x40000000); %bb.4(50.00%), %bb.3(50.00%)

  %10:vgpr_32 = PHI %4:vgpr_32, %bb.1
  dead %7:sreg_64 = SI_ELSE killed %6:sreg_64, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  S_BRANCH %bb.3

bb.3:
; predecessors: %bb.2
  successors: %bb.4(0x80000000); %bb.4(100.00%)

  %8:sreg_64 = V_CMP_EQ_U32_e64 0, killed %10:vgpr_32, implicit $exec
  dead %9:sreg_64 = SI_IF killed %8:sreg_64, %bb.4, implicit-def dead $exec, implicit-def dead $scc, implicit $exec
  S_BRANCH %bb.4

bb.4:
; predecessors: %bb.1, %bb.2, %bb.3


# End machine code for function wobble.

*** Bad machine code: Virtual register defs don't dominate all uses. ***
- function:    wobble
- v. register: %10
LLVM ERROR: Found 1 machine code errors.

opt-vgpr-live-range-verifier-error.zip

[llvmbot]

@llvm/issue-subscribers-backend-amdgpu

[ruiling]

Could you help attach the LLVM IR reproducer?

[arsenm]

There is no IR reproducer. This came out of llvm-reduce and is pretty far removed from the original IR I started with

[ruiling]

ok, could you share with me the steps (llvm-reduce command) to reproduce this .mir? That would help me better understand the context. I have concern there may be other related issues.

[ruiling]

I think the attached .mir has already break the if-else-endif structure. I can fix the vgpr-optimizer by stopping optimizing such broken case. But knowing why the situation occurs can help us to see if we can teach llvm-reduce to reduce MIR in a more reasonable way.

[arsenm]

You cannot rely on a specific block layout. If it passes the verifier, it needs to be handled correctly. It doesn't matter how the IR ended up in a certain way