clang to use the vfp instructions ,not the neon instruction for -mfpu-vfp

[ukalappa-mips]

Hi ,
We are benchmarking the ARM cortex-a9 with -mfpu=vfp ,but for the https://godbolt.org/z/5EE8h1T6b case ,we see the neon insts like

    vmul.f32        s12, s8, s6
    vmul.f32        s8, s4, s8
    vmla.f32        s12, s4, s10
    vmls.f32        s8, s10, s6
    vadd.f32        s2, s2, s12
    vadd.f32        s0, s0, s8

we trying to look for the clang/llvm switch that prevents the emission of neon instructions .

Any suggestions here ?

[llvmbot]

@llvm/issue-subscribers-backend-arm

[DavidSpickett]

I'm looking at the v7 ARMARM from https://developer.arm.com/documentation/ddi0406/latest.

I think what might be the confusion here is that there are multiple forms of vmul and friends, some that are advanced only.

For instance A8.8.352 VMUL (floating-point) has `Encoding T2/A2 VFPv2, VFPv3, VFPv4. I will double check that it's actually using that encoding however.

[ukalappa-mips]

Hi David ,

> . I will double check that it's actually using that encoding however.

Sure ,thank you ,but how about latency and pipeline dependency here ? thank you ~Umesh

…

On Thu, Oct 27, 2022 at 2:33 PM David Spickett ***@***.***> wrote: I'm looking at the v7 ARMARM from https://developer.arm.com/documentation/ddi0406/latest. I think what might be the confusion here is that there are multiple forms of vmul and friends, some that are advanced only. For instance A8.8.352 VMUL (floating-point) has `Encoding T2/A2 VFPv2, VFPv3, VFPv4. I will double check that it's actually using that encoding however. — Reply to this email directly, view it on GitHub <#58645 (comment)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AYY5RH72XDMJQBENI7R4J5DWFJAPTANCNFSM6AAAAAARPY6NU4> . You are receiving this because you authored the thread.Message ID: ***@***.***>

[DavidSpickett]

clang certainly thinks vmul.f32 requires only VFPv2: https://godbolt.org/z/YzzsxKdo3

      74: ee246a03      vmul.f32        s12, s8, s6
      78: ee224a04      vmul.f32        s8, s4, s8
      7c: ee026a05      vmla.f32        s12, s4, s10
      80: ee054a43      vmls.f32        s8, s10, s6
      84: ee311a06      vadd.f32        s2, s2, s12
      88: ee300a04      vadd.f32        s0, s0, s8

Just checking the first one, it is that encoding. Though the registers get shuffled.

n, d, m = 4, 6, 3

Which fits the instruction but are halved, this is because each D register has 2 S registers overlapped onto it.
(https://developer.arm.com/documentation/dui0204/g/Chdidbba)

You could check the others but I think at least by the manual, this is fine.

(forgive me if you knew some of this already, mostly making my process clear in case you know better than I do :) )

[DavidSpickett]

Sure ,thank you ,but how about latency and pipeline dependency here ?

This is unfortunately out of my expertise. I would suggest looking at the Cortex A9 reference manuals as well as the Armv7 ARMARM as a starting point.

I did find https://developer.arm.com/documentation/ddi0408/g/Introduction/About-the-FPU which has some references to latency also (in the PDF version).

Newer processors come with an optimisation manual, I'm not sure that the Cortex A9 did.

Otherwise I would try one of Arm's own channels e.g. https://community.arm.com/support-forums/f/architectures-and-processors-forum

I will close this issue as I don't think clang is mistaken here. Please do raise another issue if you find anything else suspicious.

[ukalappa-mips]

@DavidSpickett ,https://godbolt.org/z/qGfsr6G9z ,you mean -mfpu=vfp is defaulted to vfpv2 https://godbolt.org/z/qGfsr6G9z ?

just background we are coming from GCC world .

[DavidSpickett]

I'll spare the details but this where they get mapped

llvm-project/llvm/include/llvm/Support/ARMTargetParser.def

Line 20 in 66baa34

ARM_FPU("vfp", FK_VFP, FPUVersion::VFPV2, NeonSupportLevel::None, FPURestriction::None)

and you are right that it maps to VFPv2 (maybe there is a v1 but clang doesn't mention it).

You should also be aware that clang's -mfpu does not support setting the FPU implicitly by the cpu name or by using -mpfu=auto for ARM targets.

If you specify an FPU, as you have, it should all work the same as GCC. This has been a long standing difference that we would like to address eventually.

[DavidSpickett]

A tip for future is that clang supports -### as GCC does for example:

$ ./bin/clang -target arm-arm-none-eabi -march=armv7-a -mfpu=vfp /tmp/test.c -###

You'll see:

"-target-feature" "+vfp2" "-target-feature" "+vfp2sp" "-target-feature" "-vfp3"

+foo adds the feature and -foo removes the feature. Using this you can confirm you have exactly what you intended.

[ukalappa-mips]

@DavidSpickett ,thank you for the reference and when we are trying the switches like -mcpu=cortex-a9 ,the clang won't generate the vmla or any fused insts .

https://godbolt.org/z/jW656584Y