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[x86] backend (SDAG) asserts: "llvm/lib/IR/Constants.cpp:3071: llvm::APInt llvm::ConstantDataSequential::getElementAsAPInt(unsigned int) const: Assertion isa<IntegerType>(getElementType()) && "Accessor can only be used when element is an integer"' failed. #62995

@joker-eph

Description

@joker-eph

Reproduce with

bin/llc -mtriple=x86_64-unknown-linux-gnu -mcpu="znver4" test.ll

test.ll.txt

The constant in LLVM IR is: <2 x float> <float 1.000000e+00, float 2.000000e+00>.

The LLVM backend seems to assume that the elements in ConstantDataSequential are necessarily integers, and getElementAsAPInt() asserts.

    if (auto *CDS = dyn_cast<ConstantDataSequential>(Cst)) {
      Type *Ty = CDS->getType();
      Mask = APInt::getZero(Ty->getPrimitiveSizeInBits());
      unsigned EltBits = CDS->getElementType()->getPrimitiveSizeInBits();
      for (unsigned I = 0, E = CDS->getNumElements(); I != E; ++I)
        Mask.insertBits(CDS->getElementAsAPInt(I), I * EltBits);
      return true;
    }

Backtrace below:

#12 0x000055d055d80acb llvm::ConstantDataSequential::getElementAsAPInt(unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/IR/Constants.cpp:0:3
#13 0x000055d054a37a4b getTargetConstantBitsFromNode(llvm::SDValue, unsigned int, llvm::APInt&, llvm::SmallVectorImpl<llvm::APInt>&, bool, bool)::$_119::operator()(llvm::Constant const*, llvm::APInt&, llvm::APInt&, unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:7458:30
#14 0x000055d054933640 getTargetConstantBitsFromNode(llvm::SDValue, unsigned int, llvm::APInt&, llvm::SmallVectorImpl<llvm::APInt>&, bool, bool) /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:7532:11
#15 0x000055d0549e6d56 llvm::X86TargetLowering::computeKnownBitsForTargetNode(llvm::SDValue, llvm::KnownBits&, llvm::APInt const&, llvm::SelectionDAG const&, unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:38965:9
#16 0x000055d056894438 llvm::TargetLowering::SimplifyDemandedBitsForTargetNode(llvm::SDValue, llvm::APInt const&, llvm::APInt const&, llvm::KnownBits&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3561:3
#17 0x000055d0549f726b llvm::X86TargetLowering::SimplifyDemandedBitsForTargetNode(llvm::SDValue, llvm::APInt const&, llvm::APInt const&, llvm::KnownBits&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:44181:3
#18 0x000055d05688b2aa llvm::TargetLowering::SimplifyDemandedBits(llvm::SDValue, llvm::APInt const&, llvm::APInt const&, llvm::KnownBits&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int, bool) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2713:11
#19 0x000055d05688eb09 llvm::TargetLowering::SimplifyDemandedVectorElts(llvm::SDValue, llvm::APInt const&, llvm::APInt&, llvm::APInt&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int, bool) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2951:13
#20 0x000055d056892161 llvm::TargetLowering::SimplifyDemandedVectorElts(llvm::SDValue, llvm::APInt const&, llvm::APInt&, llvm::APInt&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int, bool) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3358:9
#21 0x000055d0549eeb5e llvm::X86TargetLowering::SimplifyDemandedVectorEltsForTargetNode(llvm::SDValue, llvm::APInt const&, llvm::APInt&, llvm::APInt&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int) const /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:43672:9
#22 0x000055d056892d57 llvm::TargetLowering::SimplifyDemandedVectorElts(llvm::SDValue, llvm::APInt const&, llvm::APInt&, llvm::APInt&, llvm::TargetLowering::TargetLoweringOpt&, unsigned int, bool) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:3460:11
#23 0x000055d056893506 llvm::TargetLowering::SimplifyDemandedVectorElts(llvm::SDValue, llvm::APInt const&, llvm::TargetLowering::DAGCombinerInfo&) const /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:2762:8
#24 0x000055d054a263e8 combineShuffle(llvm::SDNode*, llvm::SelectionDAG&, llvm::TargetLowering::DAGCombinerInfo&, llvm::X86Subtarget const&) /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:42907:9
#25 0x000055d0549f9f86 llvm::X86TargetLowering::PerformDAGCombine(llvm::SDNode*, llvm::TargetLowering::DAGCombinerInfo&) const /home/mamini/projects/llvm-project/llvm/lib/Target/X86/X86ISelLowering.cpp:58053:36
#26 0x000055d0564d21df (anonymous namespace)::DAGCombiner::combine(llvm::SDNode*) /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:2040:16
#27 0x000055d0564d16d8 (anonymous namespace)::DAGCombiner::Run(llvm::CombineLevel) /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:1821:18
#28 0x000055d0564d0f9f llvm::SelectionDAG::Combine(llvm::CombineLevel, llvm::AAResults*, llvm::CodeGenOpt::Level) /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:27255:3
#29 0x000055d05677e12c llvm::SelectionDAGISel::CodeGenAndEmitDAG() /home/mamini/projects/llvm-project/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp:926:3
#30 0x000055d05677cd5d 

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