```llvm ; RUN: llc -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names < %s define void @test(i32 %x, ptr %p) { %lshr = lshr i32 %x, 1 %zext = zext i32 %lshr to i48 %and = and i48 %zext, 255 store i48 %and, ptr %p ret void } ``` Results in: ``` rlwinm r3, r3, 31, 24, 31 stw r3, 0(r4) blr ``` Note the missing store of the upper 16 bits. This is caused by an incorrect custom DAGCombine added in https://github.com/llvm/llvm-project/commit/b0e249d5e289dc3f7e4a7cff785453206925f8b9.