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[AMDGPU][True16][MC] fp conversion in true/fake16 format #104449

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@broxigarchen broxigarchen changed the title tmp [AMDGPU][True16][MC] fp conversion in true/fake16 format Aug 15, 2024
@broxigarchen broxigarchen force-pushed the main-merge-fake16-vop1-mc branch from d699c66 to 70f43d8 Compare August 15, 2024 16:58
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github-actions bot commented Aug 15, 2024

⚠️ C/C++ code formatter, clang-format found issues in your code. ⚠️

You can test this locally with the following command:
git-clang-format --diff eae1d65f3435b1399e1468cb27bfe745f95d4df2 e27f4509099c81992ff3787c3ae64fde78beac79 --extensions cpp -- llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
View the diff from clang-format here.
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
index ada6c3f263..9295ec77c5 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
@@ -342,8 +342,8 @@ static DecodeStatus decodeOperand_VSrcT16_Lo128(MCInst &Inst, unsigned Imm,
     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
   }
   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(
-                               OpWidth, Imm & 0xFF, false, ImmWidth,
-                               (AMDGPU::OperandSemantics)OperandSemantics));
+                              OpWidth, Imm & 0xFF, false, ImmWidth,
+                              (AMDGPU::OperandSemantics)OperandSemantics));
 }
 
 template <AMDGPUDisassembler::OpWidthTy OpWidth, unsigned ImmWidth,
@@ -360,8 +360,8 @@ static DecodeStatus decodeOperand_VSrcT16(MCInst &Inst, unsigned Imm,
     return addOperand(Inst, DAsm->createVGPR16Operand(RegIdx, IsHi));
   }
   return addOperand(Inst, DAsm->decodeNonVGPRSrcOp(
-                               OpWidth, Imm & 0xFF, false, ImmWidth,
-                               (AMDGPU::OperandSemantics)OperandSemantics));
+                              OpWidth, Imm & 0xFF, false, ImmWidth,
+                              (AMDGPU::OperandSemantics)OperandSemantics));
 }
 
 static DecodeStatus decodeOperand_KImmFP(MCInst &Inst, unsigned Imm,

@broxigarchen broxigarchen force-pushed the main-merge-fake16-vop1-mc branch from 70f43d8 to 7cc9dfa Compare August 15, 2024 17:12
@broxigarchen broxigarchen force-pushed the main-merge-fake16-vop1-mc branch from bedad2b to e27f450 Compare August 15, 2024 20:32
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