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[AMDGPU] When allocating VGPRs, VGPR spills are not part of the prologue #109439

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Merged
merged 2 commits into from
Sep 30, 2024
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[AMDGPU] When allocating VGPRs, VGPR spills are not part of the prologue #109439

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c8fbbe4
[AMDGPU] When allocating VGPRs, VGPR spills are not part of the prologue
jayfoad Sep 20, 2024
7796e26
Remove irrelevant FIXME
jayfoad Sep 30, 2024
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7 changes: 3 additions & 4 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8881,11 +8881,10 @@ bool SIInstrInfo::isBasicBlockPrologue(const MachineInstr &MI,
}

uint16_t Opcode = MI.getOpcode();
// FIXME: Copies inserted in the block prolog for live-range split should also
// be included.
return IsNullOrVectorRegister &&
(isSpill(Opcode) || (!MI.isTerminator() && Opcode != AMDGPU::COPY &&
MI.modifiesRegister(AMDGPU::EXEC, &RI)));
(isSGPRSpill(Opcode) ||
(!MI.isTerminator() && Opcode != AMDGPU::COPY &&
MI.modifiesRegister(AMDGPU::EXEC, &RI)));
}

MachineInstrBuilder
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