[SPIRV] Addition of @llvm.lround.* and @llvm.llround.* intrinsic #129240

aadeshps-mcw · 2025-02-28T13:17:13Z

--Added legalizer for @llvm.lround.* and @llvm.llround.* inrinsic
--Added Instruction Selector for @llvm.lround.* and @llvm.llround.* intrinsic
--Added tests for @llvm.lround.* and @llvm.llround.* intrinsic

github-actions · 2025-02-28T13:17:31Z

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llvmbot · 2025-02-28T13:18:04Z

@llvm/pr-subscribers-backend-spir-v

Author: Aadesh PremKumar (aadeshps-mcw)

Changes

--Added legalizer for @llvm.lround.* and @llvm.llround.* inrinsic
--Added Instruction Selector for @llvm.lround.* and @llvm.llround.* intrinsic
--Added tests for @llvm.lround.* and @llvm.llround.* intrinsic

Full diff: https://github.com/llvm/llvm-project/pull/129240.diff

4 Files Affected:

(modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+64-1)
(modified) llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp (+3)
(added) llvm/test/CodeGen/SPIRV/llvm-intrinsics/llround.ll (+108)
(added) llvm/test/CodeGen/SPIRV/llvm-intrinsics/lround.ll (+108)

diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index c52b67e72a88c..b3805f83221ce 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -282,6 +282,12 @@ class SPIRVInstructionSelector : public InstructionSelector {
                      GL::GLSLExtInst GLInst) const;
   bool selectExtInst(Register ResVReg, const SPIRVType *ResType,
                      MachineInstr &I, const ExtInstList &ExtInsts) const;
+  bool selectExtInstForLRound(Register ResVReg, const SPIRVType *ResType,
+                              MachineInstr &I, CL::OpenCLExtInst CLInst,
+                              GL::GLSLExtInst GLInst) const;
+  bool selectExtInstForLRound(Register ResVReg, const SPIRVType *ResType,
+                              MachineInstr &I, 
+                              const ExtInstList &ExtInsts) const;
 
   bool selectLog10(Register ResVReg, const SPIRVType *ResType,
                    MachineInstr &I) const;
@@ -622,7 +628,22 @@ bool SPIRVInstructionSelector::spvSelect(Register ResVReg,
     return selectSUCmp(ResVReg, ResType, I, true);
   case TargetOpcode::G_UCMP:
     return selectSUCmp(ResVReg, ResType, I, false);
-
+  case TargetOpcode::G_LROUND: 
+  case TargetOpcode::G_LLROUND:{
+      Register regForLround = MRI->createVirtualRegister(MRI -> getRegClass(ResVReg), "lround");
+      MRI->setRegClass(regForLround,&SPIRV::iIDRegClass);
+      GR.assignSPIRVTypeToVReg(GR.getSPIRVTypeForVReg(I.getOperand(1).getReg()), regForLround, *(I.getParent() -> getParent()));
+      bool isRounded = selectExtInstForLRound(regForLround, GR.getSPIRVTypeForVReg(regForLround), I, CL::round, GL::Round);
+      if(isRounded){
+        MachineBasicBlock &BB = *I.getParent();
+        MachineFunction &MF = *BB.getParent();
+        auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpConvertFToS))
+                      .addDef(ResVReg)
+                      .addUse(GR.getSPIRVTypeID(ResType))  
+                      .addUse(regForLround);
+      return MIB.constrainAllUses(TII, TRI, RBI);
+      }
+  }
   case TargetOpcode::G_STRICT_FMA:
   case TargetOpcode::G_FMA:
     return selectExtInst(ResVReg, ResType, I, CL::fma, GL::Fma);
@@ -961,6 +982,48 @@ bool SPIRVInstructionSelector::selectExtInst(Register ResVReg,
   }
   return false;
 }
+bool SPIRVInstructionSelector::selectExtInstForLRound(Register ResVReg,
+                                             const SPIRVType *ResType,
+                                             MachineInstr &I,
+                                             CL::OpenCLExtInst CLInst,
+                                             GL::GLSLExtInst GLInst) 
+                                             const {
+  ExtInstList ExtInsts = {{SPIRV::InstructionSet::OpenCL_std, CLInst},
+                          {SPIRV::InstructionSet::GLSL_std_450, GLInst}};
+  return selectExtInstForLRound(ResVReg, ResType, I, ExtInsts);
+}
+
+bool SPIRVInstructionSelector::selectExtInstForLRound(Register ResVReg,
+                                             const SPIRVType *ResType,
+                                             MachineInstr &I,
+                                             const ExtInstList &Insts) 
+                                             const {
+
+  for (const auto &Ex : Insts) {
+    SPIRV::InstructionSet::InstructionSet Set = Ex.first;
+    uint32_t Opcode = Ex.second;
+    if (STI.canUseExtInstSet(Set)) {
+      MachineBasicBlock &BB = *I.getParent();
+      auto MIB = BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpExtInst))
+                     .addDef(ResVReg)
+                     .addUse(GR.getSPIRVTypeID(ResType))
+                     .addImm(static_cast<uint32_t>(Set))
+                     .addImm(Opcode);
+      const unsigned NumOps = I.getNumOperands();
+      unsigned Index = 1;
+      if (Index < NumOps &&
+          I.getOperand(Index).getType() ==
+              MachineOperand::MachineOperandType::MO_IntrinsicID)
+        Index = 2;
+      for (; Index < NumOps; ++Index)
+        MIB.add(I.getOperand(Index));
+      MIB.constrainAllUses(TII, TRI, RBI);
+      return true;
+    }
+  }
+  return false;
+}
+
 
 bool SPIRVInstructionSelector::selectOpWithSrcs(Register ResVReg,
                                                 const SPIRVType *ResType,
diff --git a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
index daa8ea52ffe03..6bce01309cc60 100644
--- a/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVLegalizerInfo.cpp
@@ -305,6 +305,9 @@ SPIRVLegalizerInfo::SPIRVLegalizerInfo(const SPIRVSubtarget &ST) {
       {G_UADDO, G_SADDO, G_USUBO, G_SSUBO, G_UMULO, G_SMULO})
       .alwaysLegal();
 
+    getActionDefinitionsBuilder({G_LROUND, G_LLROUND})
+    .legalForCartesianProduct(allFloatScalarsAndVectors, allIntScalarsAndVectors);
+
   // FP conversions.
   getActionDefinitionsBuilder({G_FPTRUNC, G_FPEXT})
       .legalForCartesianProduct(allFloatScalarsAndVectors);
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llround.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llround.ll
new file mode 100644
index 0000000000000..7794a6ed46b0b
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/llround.ll
@@ -0,0 +1,108 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+ 
+
+  
+; CHECK:          [[opencl:%[0-9]+]] = OpExtInstImport "OpenCL.std"
+; CHECK-DAG:      [[f32:%[0-9]+]] = OpTypeFloat 32
+; CHECK-DAG:      [[i32:%[0-9]+]] = OpTypeInt 32 0
+; CHECK-DAG:      [[f64:%[0-9]+]] = OpTypeFloat 64
+; CHECK-DAG:      [[i64:%[0-9]+]] = OpTypeInt 64 0
+; CHECK-DAG:      [[vecf32:%[0-9]+]] = OpTypeVector [[f32]]
+; CHECK-DAG:      [[veci32:%[0-9]+]] = OpTypeVector [[i32]]
+; CHECK-DAG:      [[vecf64:%[0-9]+]] = OpTypeVector [[f64]]
+; CHECK-DAG:      [[veci64:%[0-9]+]] = OpTypeVector [[i64]]
+
+; CHECK:      [[rounded_i32_f32:%[0-9]+]] = OpExtInst [[f32]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[i32]] [[rounded_i32_f32]]
+; CHECK:      [[rounded_i32_f64:%[0-9]+]] = OpExtInst [[f64]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[i32]] [[rounded_i32_f64]]
+; CHECK:      [[rounded_i64_f32:%[0-9]+]] = OpExtInst [[f32]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[i64]] [[rounded_i64_f32]]
+; CHECK:      [[rounded_i64_f64:%[0-9]+]] = OpExtInst [[f64]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[i64]] [[rounded_i64_f64]]
+; CHECK:      [[rounded_v4i32_f32:%[0-9]+]] = OpExtInst [[vecf32]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[veci32]] [[rounded_v4i32_f32]]
+; CHECK:      [[rounded_v4i32_f64:%[0-9]+]] = OpExtInst [[vecf64]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[veci32]] [[rounded_v4i32_f64]]
+; CHECK:      [[rounded_v4i64_f32:%[0-9]+]] = OpExtInst [[vecf32]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[veci64]] [[rounded_v4i64_f32]]
+; CHECK:      [[rounded_v4i64_f64:%[0-9]+]] = OpExtInst [[vecf64]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[veci64]] [[rounded_v4i64_f64]]
+
+ 
+target triple = "spir64-unknown-unknown"
+ 
+define spir_func i32 @test_llround_i32_f32(float %arg0) {
+entry:
+
+  %0 = call i32 @llvm.llround.i32.f32(float %arg0)
+  ret i32 %0
+}
+
+define spir_func i32 @test_llround_i32_f64(double %arg0) {
+entry:
+
+
+  %0 = call i32 @llvm.llround.i32.f64(double %arg0)
+  ret i32 %0
+}
+ 
+define spir_func i64 @test_llround_i64_f32(float %arg0) {
+entry:
+
+
+  %0 = call i64 @llvm.llround.i64.f32(float %arg0)
+  ret i64 %0
+}
+
+define spir_func i64 @test_llround_i64_f64(double %arg0) {
+entry:
+
+
+  %0 = call i64 @llvm.llround.i64.f64(double %arg0)
+  ret i64 %0
+}
+
+define spir_func <4 x i32> @test_llround_v4i32_f32(<4 x float> %arg0) {
+entry:
+
+
+  %0 = call <4 x i32> @llvm.llround.v4i32.f32(<4 x float> %arg0)
+  ret <4 x i32> %0
+}
+
+
+define spir_func <4 x i32> @test_llround_v4i32_f64(<4 x double> %arg0) {
+entry:
+
+
+  %0 = call <4 x i32> @llvm.llround.v4i32.f64(<4 x double> %arg0)
+  ret <4 x i32> %0
+}
+
+define spir_func <4 x i64> @test_llround_v4i64_f32(<4 x float> %arg0) {
+entry:
+
+
+  %0 = call <4 x i64> @llvm.llround.v4i64.f32(<4 x float> %arg0)
+  ret <4 x i64> %0
+}
+
+
+define spir_func <4 x i64> @test_llround_v4i64_f64(<4 x double> %arg0) {
+entry:
+
+  %0 = call <4 x i64> @llvm.llround.v4i64.f64(<4 x double> %arg0)
+  ret <4 x i64> %0
+}
+ 
+declare i32 @llvm.llround.i32.f32(float)
+declare i32 @llvm.llround.i32.f64(double)
+declare i64 @llvm.llround.i64.f32(float)
+declare i64 @llvm.llround.i64.f64(double)
+
+declare <4 x i32> @llvm.llround.v4i32.f32(<4 x float>)
+declare <4 x i32> @llvm.llround.v4i32.f64(<4 x double>)
+declare <4 x i64> @llvm.llround.v4i64.f32(<4 x float>)
+declare <4 x i64> @llvm.llround.v4i64.f64(<4 x double>)
\ No newline at end of file
diff --git a/llvm/test/CodeGen/SPIRV/llvm-intrinsics/lround.ll b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/lround.ll
new file mode 100644
index 0000000000000..34060c62c5ed2
--- /dev/null
+++ b/llvm/test/CodeGen/SPIRV/llvm-intrinsics/lround.ll
@@ -0,0 +1,108 @@
+; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s
+; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %}
+ 
+
+  
+; CHECK:          [[opencl:%[0-9]+]] = OpExtInstImport "OpenCL.std"
+; CHECK-DAG:      [[f32:%[0-9]+]] = OpTypeFloat 32
+; CHECK-DAG:      [[i32:%[0-9]+]] = OpTypeInt 32 0
+; CHECK-DAG:      [[f64:%[0-9]+]] = OpTypeFloat 64
+; CHECK-DAG:      [[i64:%[0-9]+]] = OpTypeInt 64 0
+; CHECK-DAG:      [[vecf32:%[0-9]+]] = OpTypeVector [[f32]]
+; CHECK-DAG:      [[veci32:%[0-9]+]] = OpTypeVector [[i32]]
+; CHECK-DAG:      [[vecf64:%[0-9]+]] = OpTypeVector [[f64]]
+; CHECK-DAG:      [[veci64:%[0-9]+]] = OpTypeVector [[i64]]
+
+; CHECK:      [[rounded_i32_f32:%[0-9]+]] = OpExtInst [[f32]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[i32]] [[rounded_i32_f32]]
+; CHECK:      [[rounded_i32_f64:%[0-9]+]] = OpExtInst [[f64]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[i32]] [[rounded_i32_f64]]
+; CHECK:      [[rounded_i64_f32:%[0-9]+]] = OpExtInst [[f32]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[i64]] [[rounded_i64_f32]]
+; CHECK:      [[rounded_i64_f64:%[0-9]+]] = OpExtInst [[f64]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[i64]] [[rounded_i64_f64]]
+; CHECK:      [[rounded_v4i32_f32:%[0-9]+]] = OpExtInst [[vecf32]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[veci32]] [[rounded_v4i32_f32]]
+; CHECK:      [[rounded_v4i32_f64:%[0-9]+]] = OpExtInst [[vecf64]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[veci32]] [[rounded_v4i32_f64]]
+; CHECK:      [[rounded_v4i64_f32:%[0-9]+]] = OpExtInst [[vecf32]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[veci64]] [[rounded_v4i64_f32]]
+; CHECK:      [[rounded_v4i64_f64:%[0-9]+]] = OpExtInst [[vecf64]] [[opencl]] round %[[#]]
+; CHECK-NEXT:      %[[#]] = OpConvertFToS [[veci64]] [[rounded_v4i64_f64]]
+
+ 
+target triple = "spir64-unknown-unknown"
+ 
+define spir_func i32 @test_lround_i32_f32(float %arg0) {
+entry:
+
+  %0 = call i32 @llvm.lround.i32.f32(float %arg0)
+  ret i32 %0
+}
+
+define spir_func i32 @test_lround_i32_f64(double %arg0) {
+entry:
+
+
+  %0 = call i32 @llvm.lround.i32.f64(double %arg0)
+  ret i32 %0
+}
+ 
+define spir_func i64 @test_lround_i64_f32(float %arg0) {
+entry:
+
+
+  %0 = call i64 @llvm.lround.i64.f32(float %arg0)
+  ret i64 %0
+}
+
+define spir_func i64 @test_lround_i64_f64(double %arg0) {
+entry:
+
+
+  %0 = call i64 @llvm.lround.i64.f64(double %arg0)
+  ret i64 %0
+}
+
+define spir_func <4 x i32> @test_lround_v4i32_f32(<4 x float> %arg0) {
+entry:
+
+
+  %0 = call <4 x i32> @llvm.lround.v4i32.f32(<4 x float> %arg0)
+  ret <4 x i32> %0
+}
+
+
+define spir_func <4 x i32> @test_lround_v4i32_f64(<4 x double> %arg0) {
+entry:
+
+
+  %0 = call <4 x i32> @llvm.lround.v4i32.f64(<4 x double> %arg0)
+  ret <4 x i32> %0
+}
+
+define spir_func <4 x i64> @test_lround_v4i64_f32(<4 x float> %arg0) {
+entry:
+
+
+  %0 = call <4 x i64> @llvm.lround.v4i64.f32(<4 x float> %arg0)
+  ret <4 x i64> %0
+}
+
+
+define spir_func <4 x i64> @test_lround_v4i64_f64(<4 x double> %arg0) {
+entry:
+
+  %0 = call <4 x i64> @llvm.lround.v4i64.f64(<4 x double> %arg0)
+  ret <4 x i64> %0
+}
+ 
+declare i32 @llvm.lround.i32.f32(float)
+declare i32 @llvm.lround.i32.f64(double)
+declare i64 @llvm.lround.i64.f32(float)
+declare i64 @llvm.lround.i64.f64(double)
+
+declare <4 x i32> @llvm.lround.v4i32.f32(<4 x float>)
+declare <4 x i32> @llvm.lround.v4i32.f64(<4 x double>)
+declare <4 x i64> @llvm.lround.v4i64.f32(<4 x float>)
+declare <4 x i64> @llvm.lround.v4i64.f64(<4 x double>)
\ No newline at end of file

github-actions · 2025-03-05T16:23:56Z

✅ With the latest revision this PR passed the C/C++ code formatter.

aadeshps-mcw · 2025-03-17T04:02:23Z

Ping

michalpaszkowski · 2025-04-29T11:37:07Z

Thanks for the PR, synced with main branch to check the current status of tests (waiting for the results), but the change looks good overall.

aadeshps-mcw · 2025-05-05T08:15:41Z

Ping

aadeshps-mcw · 2025-05-15T03:47:55Z

Ping

MrSidims · 2025-05-15T17:02:43Z

llvm/test/CodeGen/SPIRV/llvm-intrinsics/llround.ll

nit: please remove empty lines like this

MrSidims · 2025-05-15T17:03:01Z

llvm/test/CodeGen/SPIRV/llvm-intrinsics/llround.ll

lets remove EOF symbol

MrSidims · 2025-05-15T17:04:29Z

llvm/test/CodeGen/SPIRV/llvm-intrinsics/llround.ll

@maarquitos14 please advise, which triple should be used for vulkan and opencl

Ideally, we should go with spirv64-unknown-unknown-opencl for opencl and spirv64-unknown-vulkan for vulkan.

Why vulkan is the OS component of the target triple, but OpenCL is the environment? I think they must be the same component.

I asked Google folks about that a while ago, this was their response:

To understand this part, we must look at the DXIL/HLSL triple: HLSL uses the OS part to define the shader model, and the Env to define the shader type. Example: - dxil-pc-shadermodel6.6-pixel - dxil-pc-shadermodel6.5-compute So to have a similar model, we used the OS part for vulkan: - spirv-unknown-vulkan1.3-pixel - spirv-unknown-vulkan1.3-compute If you switch vulkan to the environment, we would need to move the pixel/compute/library/vertex to another part.

Regarding OpenCL, it was introduced as an environment for something completely unrelated to SPIRV.

As I mentioned here, OpenCL should also be OS component.

How should I proceed with testing this intrinsic further?

As I mentioned here, OpenCL should also be OS component.

We are aware, @MrSidims asked the original author in #78655 (comment), but we had no answer yet. I can try and address that in a future PR, but for now, this is the current status of things.

I'm okay with cleaning things up in the future.
I interpreted Ideally in your previous comment as the current state of things doesn't require any improvements.

Ah, I see. I said ideally because for opencl spirv64-unknown-unknown should work, but I'd prefer to start having opencl explicitly in the triples, so that somebody reading the tests doesn't have to guess if it's intended for OpenCL or Vulkan. Sorry for the confusion.

MrSidims · 2025-05-15T17:08:03Z

llvm/test/CodeGen/SPIRV/llvm-intrinsics/llround.ll

Suggested change

MrSidims · 2025-05-15T17:25:30Z

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

Can it ever be false? if yes, we should prevent fallthrough

MrSidims · 2025-05-15T17:30:00Z

llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp

lets remove an empty line

Suggested change

const ExtInstList &Insts) const {

const ExtInstList &Insts) const {

aadeshps-mcw · 2025-06-05T05:13:29Z

Ping

michalpaszkowski · 2025-08-03T20:21:56Z

@MrSidims, could you please also check this PR with the DPC++ E2E test suite in the intel/llvm repository?

MrSidims · 2025-08-04T10:37:07Z

@aadeshps-mcw lets avoid squashing and force pushing for the next PRs. It's quite hard to understand, what has changed between previous and current revisions.

MrSidims · 2025-08-04T12:05:36Z

@michalpaszkowski haven't checked on GPU, but SYCL E2E CPU pass rates haven't changed in neither direction.

MrSidims

LGTM

github-actions · 2025-09-25T15:33:02Z

@aadeshps-mcw Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

Your changes will be combined with recent changes from other authors, then tested by our build bots. If there is a problem with a build, you may receive a report in an email or a comment on this PR.

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If you don't get any reports, no action is required from you. Your changes are working as expected, well done!

…m#129240) --Added legalizer for @llvm.lround.* and @llvm.llround.* inrinsic --Added Instruction Selector for @llvm.lround.* and @llvm.llround.* intrinsic --Added tests for @llvm.lround.* and @llvm.llround.* intrinsic

llvmbot added the backend:SPIR-V label Feb 28, 2025

aadeshps-mcw force-pushed the aadesh branch from a74ef4e to c5dadbc Compare March 6, 2025 08:42

aadeshps-mcw changed the title ~~Addition of @llvm.lround.* and @llvm.llround.* intrinsic~~ [SPIRV] Addition of @llvm.lround.* and @llvm.llround.* intrinsic Mar 6, 2025

MrSidims reviewed May 15, 2025

View reviewed changes

--Added lround and llround intrinsic

35135da

aadeshps-mcw force-pushed the aadesh branch from 24ad081 to 35135da Compare May 30, 2025 04:44

Merge branch 'main' into aadesh

9031278

michalpaszkowski requested a review from MrSidims August 3, 2025 20:22

MrSidims requested a review from michalpaszkowski September 22, 2025 12:55

MrSidims approved these changes Sep 22, 2025

View reviewed changes

MrSidims merged commit 78428ce into llvm:main Sep 25, 2025
10 checks passed

	const ExtInstList &Insts) const {
	const ExtInstList &Insts) const {

[SPIRV] Addition of @llvm.lround.* and @llvm.llround.* intrinsic #129240

[SPIRV] Addition of @llvm.lround.* and @llvm.llround.* intrinsic #129240

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