[SelectionDAG] Do partial reduction lowering using ISD nodes #129268
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Add lowering in tablegen for PARTIAL_REDUCE_U/SMLA ISD nodes. Only happens when the combine has been performed on the ISD node. Also adds in check to only do the DAG combine when the node can then eventually be lowered, so changes neon tests too.
Implement proper splitting functions for PARTIAL_REDUCE_MLA ISD nodes. This makes the udot_8to64 and sdot_8to64 tests generate dot product instructions for when the new ISD nodes are used.
Generic DAG combine for ISD::PARTIAL_REDUCE_U/SMLA to convert: PARTIAL_REDUCE_*MLA(Acc, ZEXT(UnextOp1), Splat(1)) into PARTIAL_REDUCE_UMLA(Acc, UnextOp1, TRUNC(Splat(1))) and PARTIAL_REDUCE_*MLA(Acc, SEXT(UnextOp1), Splat(1)) into PARTIAL_REDUCE_SMLA(Acc, UnextOp1, TRUNC(Splat(1))).
Add lowering for PARTIAL_REDUCE_U/SMLA nodes to USDOT instructions. This happens when there is a MUL instruction as the second operand in the ISD node. Then the extends on the operands of the MUL op need to have a different signedness.
…REDUCE_*MLA ISD nodes Lowering for fixed width vectors added to tablegen. There is also custom lowering to ensure that the USDOT patterns are still lowered for fixed width vectors. It also ensures that the v16i8 -> v4i64 partial reduction case is lowered here instead of being split (as there is not a v2i64 dot product instruction).
When the input type has twice the number of lanes as the output type, then the PARTIAL_REDUCE_MLA ISD node will be lowered to a pair of wide add instructions.
Remove the command line flag that decides whether partial reductions should be lowered using the PARTIAL_REDUCE_MLA ISD nodes or not.
JamesChesterman
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Series of patches that together produce a new method of lowering partial reduction intrinsics. They transform them into ISD nodes, which are then combined and lowered appropriately.