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[RISCV] Add support for -mtune=andes-45-series #142900

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Merged
merged 1 commit into from
Jun 6, 2025
Merged

[RISCV] Add support for -mtune=andes-45-series #142900

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2 changes: 2 additions & 0 deletions clang/test/Misc/target-invalid-cpu-note/riscv.c
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Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,7 @@
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr3-rv32
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr4-rv32
// TUNE-RISCV32-SAME: {{^}}, syntacore-scr5-rv32
// TUNE-RISCV32-SAME: {{^}}, andes-45-series
// TUNE-RISCV32-SAME: {{^}}, generic
// TUNE-RISCV32-SAME: {{^}}, generic-ooo
// TUNE-RISCV32-SAME: {{^}}, rocket
Expand Down Expand Up @@ -114,6 +115,7 @@
// TUNE-RISCV64-SAME: {{^}}, veyron-v1
// TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
// TUNE-RISCV64-SAME: {{^}}, andes-45-series
// TUNE-RISCV64-SAME: {{^}}, generic
// TUNE-RISCV64-SAME: {{^}}, generic-ooo
// TUNE-RISCV64-SAME: {{^}}, rocket
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1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.md
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Expand Up @@ -209,6 +209,7 @@ Changes to the RISC-V Backend
* `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.
* The `Shlcofideleg` extension was added.
* `-mcpu=sifive-x390` was added.
* `-mtune=andes-45-series` was added.

Changes to the WebAssembly Backend
----------------------------------
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3 changes: 3 additions & 0 deletions llvm/lib/Target/RISCV/RISCVProcessors.td
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Expand Up @@ -722,6 +722,9 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
FeatureStdExtZbc,
FeatureVendorXAndesPerf]>;

def ANDES_45 : RISCVTuneProcessorModel<"andes-45-series",
Andes45Model>;

def ANDES_N45 : RISCVProcessorModel<"andes-n45",
Andes45Model,
[Feature32Bit,
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