[Hexagon] Enable similar behavior for max min ISD nodes #146366
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@llvm/pr-subscribers-backend-hexagon Author: Santanu Das (quic-santdas) ChangesThis patch enables FMINUMUM/FMAXIMUMNUM to have same behavior as FMINNUM/FMAXNUM. The reason is that calling fminf and fmaxf in tern calls sfmin and sfmax respectively. This may result in an extra call stack formation which this patch tries to avoid. Full diff: https://github.com/llvm/llvm-project/pull/146366.diff 6 Files Affected:
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
index 6534ae938fede..bc1aa9dbbae05 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLowering.cpp
@@ -1493,9 +1493,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
// - indexed loads and stores (pre-/post-incremented),
// - ANY_EXTEND_VECTOR_INREG, ATOMIC_CMP_SWAP_WITH_SUCCESS, CONCAT_VECTORS,
// ConstantFP, FCEIL, FCOPYSIGN, FEXP, FEXP2, FFLOOR, FGETSIGN,
- // FLOG, FLOG2, FLOG10, FMAXIMUMNUM, FMINIMUMNUM, FNEARBYINT, FRINT, FROUND,
- // TRAP, FTRUNC, PREFETCH, SIGN_EXTEND_VECTOR_INREG,
- // ZERO_EXTEND_VECTOR_INREG,
+ // FLOG, FLOG2, FLOG10, FMAXIMUMNUM, FMAXNUM, FMINIMUMNUM, FMINNUM
+ // FNEARBYINT, FRINT, FROUND, TRAP, FTRUNC, PREFETCH,
+ // SIGN_EXTEND_VECTOR_INREG, ZERO_EXTEND_VECTOR_INREG,
// which default to "expand" for at least one type.
// Misc operations.
@@ -1648,7 +1648,7 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
ISD::FCOS, ISD::FPOW, ISD::FLOG, ISD::FLOG2,
ISD::FLOG10, ISD::FEXP, ISD::FEXP2, ISD::FCEIL, ISD::FTRUNC,
ISD::FRINT, ISD::FNEARBYINT, ISD::FROUND, ISD::FFLOOR,
- ISD::FMINIMUMNUM, ISD::FMAXIMUMNUM,
+ ISD::FMINIMUMNUM, ISD::FMINNUM, ISD::FMAXIMUMNUM, ISD::FMAXNUM,
ISD::FSINCOS, ISD::FLDEXP,
// Misc:
ISD::BR_CC, ISD::SELECT_CC, ISD::ConstantPool,
@@ -1783,7 +1783,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::FDIV, MVT::f32, Custom);
setOperationAction(ISD::FMINIMUMNUM, MVT::f32, Legal);
+ setOperationAction(ISD::FMINNUM, MVT::f32, Legal);
setOperationAction(ISD::FMAXIMUMNUM, MVT::f32, Legal);
+ setOperationAction(ISD::FMAXNUM, MVT::f32, Legal);
setOperationAction(ISD::FP_TO_UINT, MVT::i1, Promote);
setOperationAction(ISD::FP_TO_UINT, MVT::i8, Promote);
@@ -1832,7 +1834,9 @@ HexagonTargetLowering::HexagonTargetLowering(const TargetMachine &TM,
}
if (Subtarget.hasV67Ops()) {
setOperationAction(ISD::FMINIMUMNUM, MVT::f64, Legal);
+ setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
setOperationAction(ISD::FMAXIMUMNUM, MVT::f64, Legal);
+ setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
setOperationAction(ISD::FMUL, MVT::f64, Legal);
}
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index fbbcacf0d713e..086832e3ed6c8 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -128,7 +128,9 @@ HexagonTargetLowering::initializeHVXLowering() {
setOperationAction(ISD::FSUB, T, Legal);
setOperationAction(ISD::FMUL, T, Legal);
setOperationAction(ISD::FMINIMUMNUM, T, Legal);
+ setOperationAction(ISD::FMINNUM, T, Legal);
setOperationAction(ISD::FMAXIMUMNUM, T, Legal);
+ setOperationAction(ISD::FMAXNUM, T, Legal);
setOperationAction(ISD::INSERT_SUBVECTOR, T, Custom);
setOperationAction(ISD::EXTRACT_SUBVECTOR, T, Custom);
@@ -165,7 +167,9 @@ HexagonTargetLowering::initializeHVXLowering() {
setOperationAction(ISD::FSUB, P, Custom);
setOperationAction(ISD::FMUL, P, Custom);
setOperationAction(ISD::FMINIMUMNUM, P, Custom);
+ setOperationAction(ISD::FMINNUM, P, Custom);
setOperationAction(ISD::FMAXIMUMNUM, P, Custom);
+ setOperationAction(ISD::FMAXNUM, P, Custom);
setOperationAction(ISD::SETCC, P, Custom);
setOperationAction(ISD::VSELECT, P, Custom);
@@ -3173,7 +3177,9 @@ HexagonTargetLowering::LowerHvxOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::FSUB:
case ISD::FMUL:
case ISD::FMINIMUMNUM:
+ case ISD::FMINNUM:
case ISD::FMAXIMUMNUM:
+ case ISD::FMAXNUM:
case ISD::MULHS:
case ISD::MULHU:
case ISD::AND:
diff --git a/llvm/lib/Target/Hexagon/HexagonPatterns.td b/llvm/lib/Target/Hexagon/HexagonPatterns.td
index 2a991bafbf148..170ef531565be 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatterns.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatterns.td
@@ -1580,7 +1580,9 @@ def: OpR_RR_pat<F2_sfadd, pf2<fadd>, f32, F32>;
def: OpR_RR_pat<F2_sfsub, pf2<fsub>, f32, F32>;
def: OpR_RR_pat<F2_sfmpy, pf2<fmul>, f32, F32>;
def: OpR_RR_pat<F2_sfmin, pf2<fminimumnum>, f32, F32>;
+def: OpR_RR_pat<F2_sfmin, pf2<fminnum>, f32, F32>;
def: OpR_RR_pat<F2_sfmax, pf2<fmaximumnum>, f32, F32>;
+def: OpR_RR_pat<F2_sfmax, pf2<fmaxnum>, f32, F32>;
let Predicates = [HasV66] in {
def: OpR_RR_pat<F2_dfadd, pf2<fadd>, f64, F64>;
@@ -1601,7 +1603,9 @@ let Predicates = [HasV67,UseUnsafeMath], AddedComplexity = 50 in {
}
let Predicates = [HasV67] in {
def: OpR_RR_pat<F2_dfmin, pf2<fminimumnum>, f64, F64>;
+ def: OpR_RR_pat<F2_dfmin, pf2<fminnum>, f64, F64>;
def: OpR_RR_pat<F2_dfmax, pf2<fmaximumnum>, f64, F64>;
+ def: OpR_RR_pat<F2_dfmax, pf2<fmaxnum>, f64, F64>;
def: Pat<(fmul F64:$Rs, F64:$Rt), (DfMpy (F2_dfmpyfix $Rs, $Rt),
(F2_dfmpyfix $Rt, $Rs))>;
diff --git a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
index ba449eaeed34c..2b1bf54be9e3f 100644
--- a/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
+++ b/llvm/lib/Target/Hexagon/HexagonPatternsHVX.td
@@ -512,6 +512,12 @@ let Predicates = [UseHVXV68, UseHVX128B, UseHVXQFloat] in {
def: OpR_RR_pat<V6_vmax_hf, pf2<fmaximumnum>, VecF16, HVF16>;
def: OpR_RR_pat<V6_vmin_sf, pf2<fminimumnum>, VecF32, HVF32>;
def: OpR_RR_pat<V6_vmax_sf, pf2<fmaximumnum>, VecF32, HVF32>;
+
+ def: OpR_RR_pat<V6_vmin_hf, pf2<fminnum>, VecF16, HVF16>;
+ def: OpR_RR_pat<V6_vmax_hf, pf2<fmaxnum>, VecF16, HVF16>;
+ def: OpR_RR_pat<V6_vmin_sf, pf2<fminnum>, VecF32, HVF32>;
+ def: OpR_RR_pat<V6_vmax_sf, pf2<fmaxnum>, VecF32, HVF32>;
+
}
let Predicates = [UseHVXV68, UseHVX128B, UseHVXIEEEFP] in {
@@ -525,6 +531,11 @@ let Predicates = [UseHVXV68, UseHVX128B, UseHVXIEEEFP] in {
def: OpR_RR_pat<V6_vfmax_hf, pf2<fmaximumnum>, VecF16, HVF16>;
def: OpR_RR_pat<V6_vfmin_sf, pf2<fminimumnum>, VecF32, HVF32>;
def: OpR_RR_pat<V6_vfmax_sf, pf2<fmaximumnum>, VecF32, HVF32>;
+
+ def: OpR_RR_pat<V6_vfmin_hf, pf2<fminnum>, VecF16, HVF16>;
+ def: OpR_RR_pat<V6_vfmax_hf, pf2<fmaxnum>, VecF16, HVF16>;
+ def: OpR_RR_pat<V6_vfmin_sf, pf2<fminnum>, VecF32, HVF32>;
+ def: OpR_RR_pat<V6_vfmax_sf, pf2<fmaxnum>, VecF32, HVF32>;
}
let Predicates = [UseHVX] in {
diff --git a/llvm/test/CodeGen/Hexagon/fminmax-v67.ll b/llvm/test/CodeGen/Hexagon/fminmax-v67.ll
index ba4fcb5afdba3..52fdedc9e6f66 100644
--- a/llvm/test/CodeGen/Hexagon/fminmax-v67.ll
+++ b/llvm/test/CodeGen/Hexagon/fminmax-v67.ll
@@ -2,7 +2,7 @@
; CHECK-LABEL: t1
-; CHECK: call fmax
+; CHECK: dfmax
define dso_local double @t1(double %a, double %b) local_unnamed_addr {
entry:
@@ -11,7 +11,7 @@ entry:
}
; CHECK-LABEL: t2
-; CHECK: call fmin
+; CHECK: dfmin
define dso_local double @t2(double %a, double %b) local_unnamed_addr {
entry:
@@ -20,7 +20,7 @@ entry:
}
; CHECK-LABEL: t3
-; CHECK: call fmaxf
+; CHECK: sfmax
define dso_local float @t3(float %a, float %b) local_unnamed_addr {
entry:
@@ -29,7 +29,7 @@ entry:
}
; CHECK-LABEL: t4
-; CHECK: call fminf
+; CHECK: sfmin
define dso_local float @t4(float %a, float %b) local_unnamed_addr {
entry:
diff --git a/llvm/test/CodeGen/Hexagon/fminmax.ll b/llvm/test/CodeGen/Hexagon/fminmax.ll
index 2aae79e6b9bf3..ff9e115ca6ebb 100644
--- a/llvm/test/CodeGen/Hexagon/fminmax.ll
+++ b/llvm/test/CodeGen/Hexagon/fminmax.ll
@@ -4,7 +4,7 @@ target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i
target triple = "hexagon"
; CHECK-LABEL: cfminf
-; CHECK: call fminf
+; CHECK: sfmin
define float @cfminf(float %x, float %y) #0 {
entry:
%call = tail call float @fminf(float %x, float %y) #1
@@ -12,7 +12,7 @@ entry:
}
; CHECK-LABEL: cfmaxf
-; CHECK: call fmaxf
+; CHECK: sfmax
define float @cfmaxf(float %x, float %y) #0 {
entry:
%call = tail call float @fmaxf(float %x, float %y) #1
@@ -20,7 +20,7 @@ entry:
}
; CHECK-LABEL: minnum
-; CHECK: call fminf
+; CHECK: sfmin
define float @minnum(float %x, float %y) #0 {
entry:
%call = tail call float @llvm.minnum.f32(float %x, float %y) #1
@@ -28,7 +28,7 @@ entry:
}
; CHECK-LABEL: maxnum
-; CHECK: call fmaxf
+; CHECK: sfmax
define float @maxnum(float %x, float %y) #0 {
entry:
%call = tail call float @llvm.maxnum.f32(float %x, float %y) #1
|
I guess the patch is doing the opposite, ie, enabling FMINNUM/FMAXNUM to have same behavior as FMINUMUMNUM/FMAXIMUMNUM. With sNaNs the behavior for FMINNUM and FMINUMUMNUM is different. The behavior was fixed recently with this patch: #139056 |
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This patch enables FMINUMUM/FMAXIMUMNUM to have same behavior as FMINNUM/FMAXNUM. The reason is that calling fminf and fmaxf in tern calls sfmin and sfmax respectively. This may result in an extra call stack formation which this patch tries to avoid.