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[PowerPC] Implement vector unpack instructions #151004

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Merged
merged 3 commits into from
Sep 2, 2025
Merged

[PowerPC] Implement vector unpack instructions #151004

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[PowerPC] Implement vector unpack instructions
lei137 Sep 2, 2025
3fe6b7d
Merge branch 'main' into vsxUnpack
lei137 Sep 2, 2025
0e9d27b
Merge branch 'main' into vsxUnpack
lei137 Sep 2, 2025
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78 changes: 78 additions & 0 deletions llvm/lib/Target/PowerPC/PPCInstrFuture.td
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Original file line number Diff line number Diff line change
Expand Up @@ -45,6 +45,67 @@ multiclass XOForm_RTAB5_L1r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
}
}

class VXForm_VRTB5<bits<11> xo, bits<5> R, dag OOL, dag IOL, string asmstr,
list<dag> pattern> : I<4, OOL, IOL, asmstr, NoItinerary> {
bits<5> VRT;
bits<5> VRB;

let Pattern = pattern;

let Inst{6 -10} = VRT;
let Inst{11 -15} = R;
let Inst{16 -20} = VRB;
let Inst{21 -31} = xo;
}

class VXForm_VRTB5_UIM2<bits<11> xo, bits<3> R, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<4, OOL, IOL, asmstr, NoItinerary> {
bits<5> VRT;
bits<5> VRB;
bits<2> UIM;

let Pattern = pattern;

let Inst{6 -10} = VRT;
let Inst{11 -13} = R;
let Inst{14 -15} = UIM;
let Inst{16 -20} = VRB;
let Inst{21 -31} = xo;
}

class VXForm_VRTB5_UIM1<bits<11> xo, bits<4> R, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<4, OOL, IOL, asmstr, NoItinerary> {
bits<5> VRT;
bits<5> VRB;
bits<1> UIM;

let Pattern = pattern;

let Inst{6 -10} = VRT;
let Inst{11 -14} = R;
let Inst{15} = UIM;
let Inst{16 -20} = VRB;
let Inst{21 -31} = xo;
}

class VXForm_VRTB5_UIM3<bits<11> xo, bits<2> R, dag OOL, dag IOL, string asmstr,
list<dag> pattern>
: I<4, OOL, IOL, asmstr, NoItinerary> {
bits<5> VRT;
bits<5> VRB;
bits<3> UIM;

let Pattern = pattern;

let Inst{6 -10} = VRT;
let Inst{11 -12} = R;
let Inst{13 -15} = UIM;
let Inst{16 -20} = VRB;
let Inst{21 -31} = xo;
}

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@diggerlin diggerlin Jul 29, 2025 •
edited
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not sure whether to a base class for above 4 class is a good idea or not ?

since there has same

bits<5> VRT;
 bits<5> VRB;
 
  let Inst{6 -10} = VRT;
 let Inst{16 -20} = VRB;
 let Inst{21 -31} = xo;

and

I<4, OOL, IOL, asmstr, NoItinerary>

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My preference is to keep them separate as the middle bits {11-16} are different combinations of fields for all of them.

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@diggerlin Actually I took another look at this and you are right, this is better defined using a base class. I have put up an NFC patch to address this: [PowerPC][NFC] Simplify vector unpacked instr classes

let Predicates = [IsISAFuture] in {
defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
(ins g8rc:$RA, g8rc:$RB, u1imm:$L),
Expand Down Expand Up @@ -81,4 +142,21 @@ let Predicates = [HasVSX, IsISAFuture] in {
(ins vsrprc:$XTp, (memr $RA):$addr, g8rc:$RB),
"stxvprll $XTp, $addr, $RB", IIC_LdStLFD, []>;
}

def VUPKHSNTOB : VXForm_VRTB5<387, 0, (outs vrrc:$VRT), (ins vrrc:$VRB),
"vupkhsntob $VRT, $VRB", []>;
def VUPKLSNTOB : VXForm_VRTB5<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB),
"vupklsntob $VRT, $VRB", []>;
def VUPKINT4TOBF16
: VXForm_VRTB5_UIM2<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM),
"vupkint4tobf16 $VRT, $VRB, $UIM", []>;
def VUPKINT8TOBF16
: VXForm_VRTB5_UIM1<387, 1, (outs vrrc:$VRT), (ins vrrc:$VRB, u1imm:$UIM),
"vupkint8tobf16 $VRT, $VRB, $UIM", []>;
def VUPKINT8TOFP32
: VXForm_VRTB5_UIM2<387, 3, (outs vrrc:$VRT), (ins vrrc:$VRB, u2imm:$UIM),
"vupkint8tofp32 $VRT, $VRB, $UIM", []>;
def VUPKINT4TOFP32
: VXForm_VRTB5_UIM3<387, 2, (outs vrrc:$VRT), (ins vrrc:$VRB, u3imm:$UIM),
"vupkint4tofp32 $VRT, $VRB, $UIM", []>;
}
18 changes: 18 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -195,3 +195,21 @@

#CHECK: dmxxsha224256pad 0, 1
0xf0,0x18,0x0e,0x94

#CHECK: vupkhsntob 2, 4
0x10,0x40,0x21,0x83

#CHECK: vupklsntob 2, 4
0x10,0x41,0x21,0x83

#CHECK: vupkint4tobf16 2, 4, 3
0x10,0x4b,0x21,0x83

#CHECK: vupkint8tobf16 1, 3, 1
0x10,0x23,0x19,0x83

#CHECK: vupkint4tofp32 3, 5, 2
0x10,0x72,0x29,0x83

#CHECK: vupkint8tofp32 3, 5, 2
0x10,0x6e,0x29,0x83
18 changes: 18 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
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Expand Up @@ -189,3 +189,21 @@

#CHECK: dmxxsha224256pad 0, 1
0x94,0x0e,0x18,0xf0

#CHECK: vupkhsntob 2, 4
0x83,0x21,0x40,0x10

#CHECK: vupklsntob 2, 4
0x83,0x21,0x41,0x10

#CHECK: vupkint4tobf16 2, 4, 3
0x83,0x21,0x4b,0x10

#CHECK: vupkint8tobf16 1, 3, 1
0x83,0x19,0x23,0x10

#CHECK: vupkint4tofp32 3, 5, 2
0x83,0x29,0x72,0x10

#CHECK: vupkint8tofp32 3, 5, 2
0x83,0x29,0x6e,0x10
24 changes: 24 additions & 0 deletions llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
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Expand Up @@ -282,3 +282,27 @@
dmxxsha224256pad 0, 1
#CHECK-BE: dmxxsha224256pad 0, 1 # encoding: [0xf0,0x18,0x0e,0x94]
#CHECK-LE: dmxxsha224256pad 0, 1 # encoding: [0x94,0x0e,0x18,0xf0]

vupkhsntob 2, 4
#CHECK-BE: vupkhsntob 2, 4 # encoding: [0x10,0x40,0x21,0x83]
#CHECK-LE: vupkhsntob 2, 4 # encoding: [0x83,0x21,0x40,0x10]

vupklsntob 2, 4
#CHECK-BE: vupklsntob 2, 4 # encoding: [0x10,0x41,0x21,0x83]
#CHECK-LE: vupklsntob 2, 4 # encoding: [0x83,0x21,0x41,0x10]

vupkint4tobf16 2, 4, 3
#CHECK-BE: vupkint4tobf16 2, 4, 3 # encoding: [0x10,0x4b,0x21,0x83]
#CHECK-LE: vupkint4tobf16 2, 4, 3 # encoding: [0x83,0x21,0x4b,0x10]

vupkint8tobf16 1, 3, 1
#CHECK-BE: vupkint8tobf16 1, 3, 1 # encoding: [0x10,0x23,0x19,0x83]
#CHECK-LE: vupkint8tobf16 1, 3, 1 # encoding: [0x83,0x19,0x23,0x10]

vupkint4tofp32 3, 5, 2
#CHECK-BE: vupkint4tofp32 3, 5, 2 # encoding: [0x10,0x72,0x29,0x83]
#CHECK-LE: vupkint4tofp32 3, 5, 2 # encoding: [0x83,0x29,0x72,0x10]

vupkint8tofp32 3, 5, 2
#CHECK-BE: vupkint8tofp32 3, 5, 2 # encoding: [0x10,0x6e,0x29,0x83]
#CHECK-LE: vupkint8tofp32 3, 5, 2 # encoding: [0x83,0x29,0x6e,0x10]
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