[Target] Remove SoftFail field on targets that don't use it (NFC) #154659

s-barannikov · 2025-08-21T01:38:37Z

That is, on all targets except ARM and AArch64.
This field used to be required due to a bug, it was fixed long ago by 23423c0.

That is, on all targets except ARM and AArch64. This field used to be required due to a bug, but it was fixed long ago by 23423c0.

llvmbot · 2025-08-21T01:39:11Z

@llvm/pr-subscribers-backend-loongarch
@llvm/pr-subscribers-backend-hexagon
@llvm/pr-subscribers-backend-mips

@llvm/pr-subscribers-backend-amdgpu

Author: Sergei Barannikov (s-barannikov)

Changes

That is, on all targets except ARM and AArch64.
This field used to be required due to a bug, it was fixed long ago by 23423c0.

Patch is 39.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/154659.diff

21 Files Affected:

(modified) llvm/lib/Target/AMDGPU/AMDGPUInstructions.td (-6)
(modified) llvm/lib/Target/ARC/ARCInstrFormats.td (-1)
(modified) llvm/lib/Target/AVR/AVRInstrFormats.td (-2)
(modified) llvm/lib/Target/BPF/BPFInstrFormats.td (-1)
(modified) llvm/lib/Target/CSKY/CSKYInstrFormats.td (-1)
(modified) llvm/lib/Target/Hexagon/HexagonInstrFormats.td (-12)
(modified) llvm/lib/Target/Lanai/LanaiInstrFormats.td (-1)
(modified) llvm/lib/Target/LoongArch/LoongArchInstrFormats.td (-5)
(modified) llvm/lib/Target/MSP430/MSP430InstrFormats.td (-1)
(modified) llvm/lib/Target/Mips/MicroMipsInstrFormats.td (-1)
(modified) llvm/lib/Target/Mips/Mips16InstrFormats.td (-2)
(modified) llvm/lib/Target/Mips/MipsInstrFormats.td (-2)
(modified) llvm/lib/Target/PowerPC/PPCInstrFormats.td (-2)
(modified) llvm/lib/Target/PowerPC/PPCInstrP10.td (-1)
(modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (-7)
(modified) llvm/lib/Target/RISCV/RISCVInstrFormatsC.td (-5)
(modified) llvm/lib/Target/Sparc/SparcInstrFormats.td (-1)
(modified) llvm/lib/Target/SystemZ/SystemZInstrFormats.td (-84)
(modified) llvm/lib/Target/VE/VEInstrFormats.td (-1)
(modified) llvm/lib/Target/XCore/XCoreInstrFormats.td (-1)
(modified) llvm/lib/Target/Xtensa/XtensaInstrFormats.td (-2)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 402f5765fba47..efcd87e466207 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -34,12 +34,6 @@ class AMDGPUInst <dag outs, dag ins, string asm = "",
   let Pattern = pattern;
   let Itinerary = NullALU;
 
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<128> SoftFail = 0; // FIXME: If this is smaller than largest instruction, DecodeEmitter crashes
-
   let DecoderNamespace = Namespace;
 
   let TSFlags{63} = isRegisterLoad;
diff --git a/llvm/lib/Target/ARC/ARCInstrFormats.td b/llvm/lib/Target/ARC/ARCInstrFormats.td
index d6d2eaffab19b..bd2ed00576177 100644
--- a/llvm/lib/Target/ARC/ARCInstrFormats.td
+++ b/llvm/lib/Target/ARC/ARCInstrFormats.td
@@ -12,7 +12,6 @@
 
 class Encoding64 {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
 }
 
 // Address operands
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td b/llvm/lib/Target/AVR/AVRInstrFormats.td
index 407e14a079f3e..e1e65b56370cc 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -19,8 +19,6 @@ class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
   dag InOperandList = ins;
   let AsmString = asmstr;
   let Pattern = pattern;
-
-  field bits<32> SoftFail = 0;
 }
 
 /// A 16-bit AVR instruction.
diff --git a/llvm/lib/Target/BPF/BPFInstrFormats.td b/llvm/lib/Target/BPF/BPFInstrFormats.td
index 50cca5148de7c..ccabc5a6ae77b 100644
--- a/llvm/lib/Target/BPF/BPFInstrFormats.td
+++ b/llvm/lib/Target/BPF/BPFInstrFormats.td
@@ -111,7 +111,6 @@ def BPF_FETCH : BPFAtomicFlag<0x1>;
 class InstBPF<dag outs, dag ins, string asmstr, list<dag> pattern>
   : Instruction {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   let Size = 8;
 
   let Namespace = "BPF";
diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormats.td b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
index 8144a501b3d27..5296d282c689b 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrFormats.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
@@ -24,7 +24,6 @@ class CSKYInst<AddrMode am, int sz, dag outs, dag ins, string asmstr,
   let Namespace = "CSKY";
   int Size = sz;
   AddrMode AM = am;
-  field bits<32> SoftFail = 0;
   let OutOperandList = outs;
   let InOperandList = ins;
   let AsmString = asmstr;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
index 605064986b336..014e48cda5a11 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
@@ -60,12 +60,6 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
   let Itinerary = itin;
   let Size = 4;
 
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
-
   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 
   // Instruction type according to the ISA.
@@ -287,12 +281,6 @@ class InstDuplex<bits<4> iClass, string cstr = ""> : Instruction,
   let Itinerary = DUPLEX;
   let Size = 4;
 
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
-
   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 
   let TSFlags{6-0} = Type.Value;
diff --git a/llvm/lib/Target/Lanai/LanaiInstrFormats.td b/llvm/lib/Target/Lanai/LanaiInstrFormats.td
index 5c21d203edf26..cd36325229b1e 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrFormats.td
+++ b/llvm/lib/Target/Lanai/LanaiInstrFormats.td
@@ -9,7 +9,6 @@
 class InstLanai<dag outs, dag ins, string asmstr, list<dag> pattern>
     : Instruction {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
   let Size = 4;
 
   let Namespace = "Lanai";
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
index eee297d2e2d91..419e20431c59f 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
@@ -20,11 +20,6 @@ class LAInst<dag outs, dag ins, string opcstr, string opnstr,
              list<dag> pattern = []>
     : Instruction {
   field bits<32> Inst;
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
 
   let Namespace = "LoongArch";
   let Size = 4;
diff --git a/llvm/lib/Target/MSP430/MSP430InstrFormats.td b/llvm/lib/Target/MSP430/MSP430InstrFormats.td
index 36f40d6fc89dd..0e784aa4ff914 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrFormats.td
+++ b/llvm/lib/Target/MSP430/MSP430InstrFormats.td
@@ -31,7 +31,6 @@ def DstMem      : DestMode<1>;   // m
 // Generic MSP430 Format
 class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   let Namespace = "MSP430";
 
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
index c4c48762dbea4..f848fe6e58912 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
@@ -45,7 +45,6 @@ class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
 {
   let Size = 2;
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
   bits<6> Opcode = 0x0;
 }
 
diff --git a/llvm/lib/Target/Mips/Mips16InstrFormats.td b/llvm/lib/Target/Mips/Mips16InstrFormats.td
index b180e53855bc4..1a4bbacb48d3e 100644
--- a/llvm/lib/Target/Mips/Mips16InstrFormats.td
+++ b/llvm/lib/Target/Mips/Mips16InstrFormats.td
@@ -62,7 +62,6 @@ class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
   let Inst{15-11} = Opcode;
 
   let Size=2;
-  field bits<16> SoftFail = 0;
 }
 
 //
@@ -75,7 +74,6 @@ class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
   field bits<32> Inst;
 
   let Size=4;
-  field bits<32> SoftFail = 0;
 }
 
 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td
index 10529c7d9e192..992b3ae11a178 100644
--- a/llvm/lib/Target/Mips/MipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsInstrFormats.td
@@ -107,8 +107,6 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
   let TSFlags{6}     = hasFCCRegOperand;
 
   let DecoderNamespace = "Mips";
-
-  field bits<32> SoftFail = 0;
 }
 
 // Mips32/64 Instruction Format
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 2ced3fe80ea99..b4b475b470a56 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -13,7 +13,6 @@
 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
         : Instruction {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
   let Size = 4;
 
   bit PPC64 = 0;  // Default value, override with isPPC64
@@ -95,7 +94,6 @@ class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
          InstrItinClass itin>
         : Instruction {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   let Size = 8;
 
   bit PPC64 = 0;  // Default value, override with isPPC64
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index 98dd8464c0ac8..c4a027d65b665 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -117,7 +117,6 @@ def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,
 class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
          InstrItinClass itin> : Instruction {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   bit PCRel = 0; // Default value, set by isPCRel.
   let Size = 8;
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 878a0ec938919..c2667b0e7c9e4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -273,11 +273,6 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
              list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<32> Inst;
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
   let Size = 4;
 }
 
@@ -285,7 +280,6 @@ class RVInst48<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
   let Size = 6;
 }
 
@@ -293,7 +287,6 @@ class RVInst64<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   let Size = 8;
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 5e16061dc470f..209c3fae63f45 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -14,11 +14,6 @@ class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<16> Inst;
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<16> SoftFail = 0;
   let Size = 2;
 }
 
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 79c4cb2128a0f..3d3dfdc52eb5d 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -23,7 +23,6 @@ class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
   let Pattern = pattern;
 
   let DecoderNamespace = "Sparc";
-  field bits<32> SoftFail = 0;
 
   let Itinerary = itin;
 }
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 3e9a515bf1153..d0a549518cc45 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -188,7 +188,6 @@ def getTwoOperandOpcode : InstrMapping {
 class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
 
   let Inst = op;
 }
@@ -196,7 +195,6 @@ class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
 
   bits<8> I1;
 
@@ -207,7 +205,6 @@ class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> I1;
   bits<4> I2;
@@ -221,7 +218,6 @@ class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> M1;
   bits<12> RI2;
@@ -236,7 +232,6 @@ class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<16> I2;
@@ -250,7 +245,6 @@ class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<16> RI2;
@@ -264,7 +258,6 @@ class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> M1;
   bits<16> RI2;
@@ -278,7 +271,6 @@ class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<16> I2;
@@ -296,7 +288,6 @@ class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -315,7 +306,6 @@ class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<8> I2;
@@ -333,7 +323,6 @@ class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
@@ -350,7 +339,6 @@ class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
@@ -368,7 +356,6 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
                bits<8> I3Or = 0, bits<8> I4Or = 0>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -402,7 +389,6 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
 class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> M3;
@@ -419,7 +405,6 @@ class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<32> I2;
@@ -433,7 +418,6 @@ class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<32> RI2;
@@ -447,7 +431,6 @@ class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> M1;
   bits<32> RI2;
@@ -461,7 +444,6 @@ class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<8> I2;
@@ -481,7 +463,6 @@ class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -494,7 +475,6 @@ class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
@@ -510,7 +490,6 @@ class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -524,7 +503,6 @@ class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -541,7 +519,6 @@ class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -558,7 +535,6 @@ class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -574,7 +550,6 @@ class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -590,7 +565,6 @@ class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -607,7 +581,6 @@ class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -628,7 +601,6 @@ class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> X2;
@@ -647,7 +619,6 @@ class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<d...
[truncated]

llvmbot · 2025-08-21T01:39:12Z

@llvm/pr-subscribers-backend-powerpc

Author: Sergei Barannikov (s-barannikov)

Changes

That is, on all targets except ARM and AArch64.
This field used to be required due to a bug, it was fixed long ago by 23423c0.

Patch is 39.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/154659.diff

21 Files Affected:

(modified) llvm/lib/Target/AMDGPU/AMDGPUInstructions.td (-6)
(modified) llvm/lib/Target/ARC/ARCInstrFormats.td (-1)
(modified) llvm/lib/Target/AVR/AVRInstrFormats.td (-2)
(modified) llvm/lib/Target/BPF/BPFInstrFormats.td (-1)
(modified) llvm/lib/Target/CSKY/CSKYInstrFormats.td (-1)
(modified) llvm/lib/Target/Hexagon/HexagonInstrFormats.td (-12)
(modified) llvm/lib/Target/Lanai/LanaiInstrFormats.td (-1)
(modified) llvm/lib/Target/LoongArch/LoongArchInstrFormats.td (-5)
(modified) llvm/lib/Target/MSP430/MSP430InstrFormats.td (-1)
(modified) llvm/lib/Target/Mips/MicroMipsInstrFormats.td (-1)
(modified) llvm/lib/Target/Mips/Mips16InstrFormats.td (-2)
(modified) llvm/lib/Target/Mips/MipsInstrFormats.td (-2)
(modified) llvm/lib/Target/PowerPC/PPCInstrFormats.td (-2)
(modified) llvm/lib/Target/PowerPC/PPCInstrP10.td (-1)
(modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (-7)
(modified) llvm/lib/Target/RISCV/RISCVInstrFormatsC.td (-5)
(modified) llvm/lib/Target/Sparc/SparcInstrFormats.td (-1)
(modified) llvm/lib/Target/SystemZ/SystemZInstrFormats.td (-84)
(modified) llvm/lib/Target/VE/VEInstrFormats.td (-1)
(modified) llvm/lib/Target/XCore/XCoreInstrFormats.td (-1)
(modified) llvm/lib/Target/Xtensa/XtensaInstrFormats.td (-2)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 402f5765fba47..efcd87e466207 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -34,12 +34,6 @@ class AMDGPUInst <dag outs, dag ins, string asm = "",
   let Pattern = pattern;
   let Itinerary = NullALU;
 
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<128> SoftFail = 0; // FIXME: If this is smaller than largest instruction, DecodeEmitter crashes
-
   let DecoderNamespace = Namespace;
 
   let TSFlags{63} = isRegisterLoad;
diff --git a/llvm/lib/Target/ARC/ARCInstrFormats.td b/llvm/lib/Target/ARC/ARCInstrFormats.td
index d6d2eaffab19b..bd2ed00576177 100644
--- a/llvm/lib/Target/ARC/ARCInstrFormats.td
+++ b/llvm/lib/Target/ARC/ARCInstrFormats.td
@@ -12,7 +12,6 @@
 
 class Encoding64 {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
 }
 
 // Address operands
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td b/llvm/lib/Target/AVR/AVRInstrFormats.td
index 407e14a079f3e..e1e65b56370cc 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -19,8 +19,6 @@ class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
   dag InOperandList = ins;
   let AsmString = asmstr;
   let Pattern = pattern;
-
-  field bits<32> SoftFail = 0;
 }
 
 /// A 16-bit AVR instruction.
diff --git a/llvm/lib/Target/BPF/BPFInstrFormats.td b/llvm/lib/Target/BPF/BPFInstrFormats.td
index 50cca5148de7c..ccabc5a6ae77b 100644
--- a/llvm/lib/Target/BPF/BPFInstrFormats.td
+++ b/llvm/lib/Target/BPF/BPFInstrFormats.td
@@ -111,7 +111,6 @@ def BPF_FETCH : BPFAtomicFlag<0x1>;
 class InstBPF<dag outs, dag ins, string asmstr, list<dag> pattern>
   : Instruction {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   let Size = 8;
 
   let Namespace = "BPF";
diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormats.td b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
index 8144a501b3d27..5296d282c689b 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrFormats.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
@@ -24,7 +24,6 @@ class CSKYInst<AddrMode am, int sz, dag outs, dag ins, string asmstr,
   let Namespace = "CSKY";
   int Size = sz;
   AddrMode AM = am;
-  field bits<32> SoftFail = 0;
   let OutOperandList = outs;
   let InOperandList = ins;
   let AsmString = asmstr;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
index 605064986b336..014e48cda5a11 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
@@ -60,12 +60,6 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
   let Itinerary = itin;
   let Size = 4;
 
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
-
   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 
   // Instruction type according to the ISA.
@@ -287,12 +281,6 @@ class InstDuplex<bits<4> iClass, string cstr = ""> : Instruction,
   let Itinerary = DUPLEX;
   let Size = 4;
 
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
-
   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 
   let TSFlags{6-0} = Type.Value;
diff --git a/llvm/lib/Target/Lanai/LanaiInstrFormats.td b/llvm/lib/Target/Lanai/LanaiInstrFormats.td
index 5c21d203edf26..cd36325229b1e 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrFormats.td
+++ b/llvm/lib/Target/Lanai/LanaiInstrFormats.td
@@ -9,7 +9,6 @@
 class InstLanai<dag outs, dag ins, string asmstr, list<dag> pattern>
     : Instruction {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
   let Size = 4;
 
   let Namespace = "Lanai";
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
index eee297d2e2d91..419e20431c59f 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
@@ -20,11 +20,6 @@ class LAInst<dag outs, dag ins, string opcstr, string opnstr,
              list<dag> pattern = []>
     : Instruction {
   field bits<32> Inst;
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
 
   let Namespace = "LoongArch";
   let Size = 4;
diff --git a/llvm/lib/Target/MSP430/MSP430InstrFormats.td b/llvm/lib/Target/MSP430/MSP430InstrFormats.td
index 36f40d6fc89dd..0e784aa4ff914 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrFormats.td
+++ b/llvm/lib/Target/MSP430/MSP430InstrFormats.td
@@ -31,7 +31,6 @@ def DstMem      : DestMode<1>;   // m
 // Generic MSP430 Format
 class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   let Namespace = "MSP430";
 
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
index c4c48762dbea4..f848fe6e58912 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
@@ -45,7 +45,6 @@ class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
 {
   let Size = 2;
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
   bits<6> Opcode = 0x0;
 }
 
diff --git a/llvm/lib/Target/Mips/Mips16InstrFormats.td b/llvm/lib/Target/Mips/Mips16InstrFormats.td
index b180e53855bc4..1a4bbacb48d3e 100644
--- a/llvm/lib/Target/Mips/Mips16InstrFormats.td
+++ b/llvm/lib/Target/Mips/Mips16InstrFormats.td
@@ -62,7 +62,6 @@ class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
   let Inst{15-11} = Opcode;
 
   let Size=2;
-  field bits<16> SoftFail = 0;
 }
 
 //
@@ -75,7 +74,6 @@ class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
   field bits<32> Inst;
 
   let Size=4;
-  field bits<32> SoftFail = 0;
 }
 
 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td
index 10529c7d9e192..992b3ae11a178 100644
--- a/llvm/lib/Target/Mips/MipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsInstrFormats.td
@@ -107,8 +107,6 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
   let TSFlags{6}     = hasFCCRegOperand;
 
   let DecoderNamespace = "Mips";
-
-  field bits<32> SoftFail = 0;
 }
 
 // Mips32/64 Instruction Format
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 2ced3fe80ea99..b4b475b470a56 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -13,7 +13,6 @@
 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
         : Instruction {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
   let Size = 4;
 
   bit PPC64 = 0;  // Default value, override with isPPC64
@@ -95,7 +94,6 @@ class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
          InstrItinClass itin>
         : Instruction {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   let Size = 8;
 
   bit PPC64 = 0;  // Default value, override with isPPC64
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index 98dd8464c0ac8..c4a027d65b665 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -117,7 +117,6 @@ def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,
 class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
          InstrItinClass itin> : Instruction {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   bit PCRel = 0; // Default value, set by isPCRel.
   let Size = 8;
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 878a0ec938919..c2667b0e7c9e4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -273,11 +273,6 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
              list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<32> Inst;
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
   let Size = 4;
 }
 
@@ -285,7 +280,6 @@ class RVInst48<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
   let Size = 6;
 }
 
@@ -293,7 +287,6 @@ class RVInst64<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   let Size = 8;
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 5e16061dc470f..209c3fae63f45 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -14,11 +14,6 @@ class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<16> Inst;
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<16> SoftFail = 0;
   let Size = 2;
 }
 
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 79c4cb2128a0f..3d3dfdc52eb5d 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -23,7 +23,6 @@ class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
   let Pattern = pattern;
 
   let DecoderNamespace = "Sparc";
-  field bits<32> SoftFail = 0;
 
   let Itinerary = itin;
 }
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 3e9a515bf1153..d0a549518cc45 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -188,7 +188,6 @@ def getTwoOperandOpcode : InstrMapping {
 class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
 
   let Inst = op;
 }
@@ -196,7 +195,6 @@ class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
 
   bits<8> I1;
 
@@ -207,7 +205,6 @@ class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> I1;
   bits<4> I2;
@@ -221,7 +218,6 @@ class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> M1;
   bits<12> RI2;
@@ -236,7 +232,6 @@ class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<16> I2;
@@ -250,7 +245,6 @@ class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<16> RI2;
@@ -264,7 +258,6 @@ class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> M1;
   bits<16> RI2;
@@ -278,7 +271,6 @@ class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<16> I2;
@@ -296,7 +288,6 @@ class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -315,7 +306,6 @@ class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<8> I2;
@@ -333,7 +323,6 @@ class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
@@ -350,7 +339,6 @@ class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
@@ -368,7 +356,6 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
                bits<8> I3Or = 0, bits<8> I4Or = 0>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -402,7 +389,6 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
 class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> M3;
@@ -419,7 +405,6 @@ class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<32> I2;
@@ -433,7 +418,6 @@ class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<32> RI2;
@@ -447,7 +431,6 @@ class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> M1;
   bits<32> RI2;
@@ -461,7 +444,6 @@ class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<8> I2;
@@ -481,7 +463,6 @@ class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -494,7 +475,6 @@ class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
@@ -510,7 +490,6 @@ class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -524,7 +503,6 @@ class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -541,7 +519,6 @@ class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -558,7 +535,6 @@ class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -574,7 +550,6 @@ class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -590,7 +565,6 @@ class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -607,7 +581,6 @@ class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -628,7 +601,6 @@ class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> X2;
@@ -647,7 +619,6 @@ class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<d...
[truncated]

llvmbot · 2025-08-21T01:39:12Z

@llvm/pr-subscribers-backend-sparc

Author: Sergei Barannikov (s-barannikov)

Changes

That is, on all targets except ARM and AArch64.
This field used to be required due to a bug, it was fixed long ago by 23423c0.

Patch is 39.06 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/154659.diff

21 Files Affected:

(modified) llvm/lib/Target/AMDGPU/AMDGPUInstructions.td (-6)
(modified) llvm/lib/Target/ARC/ARCInstrFormats.td (-1)
(modified) llvm/lib/Target/AVR/AVRInstrFormats.td (-2)
(modified) llvm/lib/Target/BPF/BPFInstrFormats.td (-1)
(modified) llvm/lib/Target/CSKY/CSKYInstrFormats.td (-1)
(modified) llvm/lib/Target/Hexagon/HexagonInstrFormats.td (-12)
(modified) llvm/lib/Target/Lanai/LanaiInstrFormats.td (-1)
(modified) llvm/lib/Target/LoongArch/LoongArchInstrFormats.td (-5)
(modified) llvm/lib/Target/MSP430/MSP430InstrFormats.td (-1)
(modified) llvm/lib/Target/Mips/MicroMipsInstrFormats.td (-1)
(modified) llvm/lib/Target/Mips/Mips16InstrFormats.td (-2)
(modified) llvm/lib/Target/Mips/MipsInstrFormats.td (-2)
(modified) llvm/lib/Target/PowerPC/PPCInstrFormats.td (-2)
(modified) llvm/lib/Target/PowerPC/PPCInstrP10.td (-1)
(modified) llvm/lib/Target/RISCV/RISCVInstrFormats.td (-7)
(modified) llvm/lib/Target/RISCV/RISCVInstrFormatsC.td (-5)
(modified) llvm/lib/Target/Sparc/SparcInstrFormats.td (-1)
(modified) llvm/lib/Target/SystemZ/SystemZInstrFormats.td (-84)
(modified) llvm/lib/Target/VE/VEInstrFormats.td (-1)
(modified) llvm/lib/Target/XCore/XCoreInstrFormats.td (-1)
(modified) llvm/lib/Target/Xtensa/XtensaInstrFormats.td (-2)

diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
index 402f5765fba47..efcd87e466207 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructions.td
@@ -34,12 +34,6 @@ class AMDGPUInst <dag outs, dag ins, string asm = "",
   let Pattern = pattern;
   let Itinerary = NullALU;
 
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<128> SoftFail = 0; // FIXME: If this is smaller than largest instruction, DecodeEmitter crashes
-
   let DecoderNamespace = Namespace;
 
   let TSFlags{63} = isRegisterLoad;
diff --git a/llvm/lib/Target/ARC/ARCInstrFormats.td b/llvm/lib/Target/ARC/ARCInstrFormats.td
index d6d2eaffab19b..bd2ed00576177 100644
--- a/llvm/lib/Target/ARC/ARCInstrFormats.td
+++ b/llvm/lib/Target/ARC/ARCInstrFormats.td
@@ -12,7 +12,6 @@
 
 class Encoding64 {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
 }
 
 // Address operands
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td b/llvm/lib/Target/AVR/AVRInstrFormats.td
index 407e14a079f3e..e1e65b56370cc 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -19,8 +19,6 @@ class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern>
   dag InOperandList = ins;
   let AsmString = asmstr;
   let Pattern = pattern;
-
-  field bits<32> SoftFail = 0;
 }
 
 /// A 16-bit AVR instruction.
diff --git a/llvm/lib/Target/BPF/BPFInstrFormats.td b/llvm/lib/Target/BPF/BPFInstrFormats.td
index 50cca5148de7c..ccabc5a6ae77b 100644
--- a/llvm/lib/Target/BPF/BPFInstrFormats.td
+++ b/llvm/lib/Target/BPF/BPFInstrFormats.td
@@ -111,7 +111,6 @@ def BPF_FETCH : BPFAtomicFlag<0x1>;
 class InstBPF<dag outs, dag ins, string asmstr, list<dag> pattern>
   : Instruction {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   let Size = 8;
 
   let Namespace = "BPF";
diff --git a/llvm/lib/Target/CSKY/CSKYInstrFormats.td b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
index 8144a501b3d27..5296d282c689b 100644
--- a/llvm/lib/Target/CSKY/CSKYInstrFormats.td
+++ b/llvm/lib/Target/CSKY/CSKYInstrFormats.td
@@ -24,7 +24,6 @@ class CSKYInst<AddrMode am, int sz, dag outs, dag ins, string asmstr,
   let Namespace = "CSKY";
   int Size = sz;
   AddrMode AM = am;
-  field bits<32> SoftFail = 0;
   let OutOperandList = outs;
   let InOperandList = ins;
   let AsmString = asmstr;
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
index 605064986b336..014e48cda5a11 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
+++ b/llvm/lib/Target/Hexagon/HexagonInstrFormats.td
@@ -60,12 +60,6 @@ class InstHexagon<dag outs, dag ins, string asmstr, list<dag> pattern,
   let Itinerary = itin;
   let Size = 4;
 
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
-
   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 
   // Instruction type according to the ISA.
@@ -287,12 +281,6 @@ class InstDuplex<bits<4> iClass, string cstr = ""> : Instruction,
   let Itinerary = DUPLEX;
   let Size = 4;
 
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
-
   // *** Must match MCTargetDesc/HexagonBaseInfo.h ***
 
   let TSFlags{6-0} = Type.Value;
diff --git a/llvm/lib/Target/Lanai/LanaiInstrFormats.td b/llvm/lib/Target/Lanai/LanaiInstrFormats.td
index 5c21d203edf26..cd36325229b1e 100644
--- a/llvm/lib/Target/Lanai/LanaiInstrFormats.td
+++ b/llvm/lib/Target/Lanai/LanaiInstrFormats.td
@@ -9,7 +9,6 @@
 class InstLanai<dag outs, dag ins, string asmstr, list<dag> pattern>
     : Instruction {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
   let Size = 4;
 
   let Namespace = "Lanai";
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
index eee297d2e2d91..419e20431c59f 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
@@ -20,11 +20,6 @@ class LAInst<dag outs, dag ins, string opcstr, string opnstr,
              list<dag> pattern = []>
     : Instruction {
   field bits<32> Inst;
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
 
   let Namespace = "LoongArch";
   let Size = 4;
diff --git a/llvm/lib/Target/MSP430/MSP430InstrFormats.td b/llvm/lib/Target/MSP430/MSP430InstrFormats.td
index 36f40d6fc89dd..0e784aa4ff914 100644
--- a/llvm/lib/Target/MSP430/MSP430InstrFormats.td
+++ b/llvm/lib/Target/MSP430/MSP430InstrFormats.td
@@ -31,7 +31,6 @@ def DstMem      : DestMode<1>;   // m
 // Generic MSP430 Format
 class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   let Namespace = "MSP430";
 
diff --git a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
index c4c48762dbea4..f848fe6e58912 100644
--- a/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MicroMipsInstrFormats.td
@@ -45,7 +45,6 @@ class MicroMipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
 {
   let Size = 2;
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
   bits<6> Opcode = 0x0;
 }
 
diff --git a/llvm/lib/Target/Mips/Mips16InstrFormats.td b/llvm/lib/Target/Mips/Mips16InstrFormats.td
index b180e53855bc4..1a4bbacb48d3e 100644
--- a/llvm/lib/Target/Mips/Mips16InstrFormats.td
+++ b/llvm/lib/Target/Mips/Mips16InstrFormats.td
@@ -62,7 +62,6 @@ class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
   let Inst{15-11} = Opcode;
 
   let Size=2;
-  field bits<16> SoftFail = 0;
 }
 
 //
@@ -75,7 +74,6 @@ class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
   field bits<32> Inst;
 
   let Size=4;
-  field bits<32> SoftFail = 0;
 }
 
 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
diff --git a/llvm/lib/Target/Mips/MipsInstrFormats.td b/llvm/lib/Target/Mips/MipsInstrFormats.td
index 10529c7d9e192..992b3ae11a178 100644
--- a/llvm/lib/Target/Mips/MipsInstrFormats.td
+++ b/llvm/lib/Target/Mips/MipsInstrFormats.td
@@ -107,8 +107,6 @@ class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
   let TSFlags{6}     = hasFCCRegOperand;
 
   let DecoderNamespace = "Mips";
-
-  field bits<32> SoftFail = 0;
 }
 
 // Mips32/64 Instruction Format
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index 2ced3fe80ea99..b4b475b470a56 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -13,7 +13,6 @@
 class I<bits<6> opcode, dag OOL, dag IOL, string asmstr, InstrItinClass itin>
         : Instruction {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
   let Size = 4;
 
   bit PPC64 = 0;  // Default value, override with isPPC64
@@ -95,7 +94,6 @@ class I2<bits<6> opcode1, bits<6> opcode2, dag OOL, dag IOL, string asmstr,
          InstrItinClass itin>
         : Instruction {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   let Size = 8;
 
   bit PPC64 = 0;  // Default value, override with isPPC64
diff --git a/llvm/lib/Target/PowerPC/PPCInstrP10.td b/llvm/lib/Target/PowerPC/PPCInstrP10.td
index 98dd8464c0ac8..c4a027d65b665 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrP10.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrP10.td
@@ -117,7 +117,6 @@ def PPClxvrzx : SDNode<"PPCISD::LXVRZX", SDT_PPCLXVRZX,
 class PI<bits<6> pref, bits<6> opcode, dag OOL, dag IOL, string asmstr,
          InstrItinClass itin> : Instruction {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   bit PCRel = 0; // Default value, set by isPCRel.
   let Size = 8;
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 878a0ec938919..c2667b0e7c9e4 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -273,11 +273,6 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
              list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<32> Inst;
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
   let Size = 4;
 }
 
@@ -285,7 +280,6 @@ class RVInst48<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
   let Size = 6;
 }
 
@@ -293,7 +287,6 @@ class RVInst64<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<64> Inst;
-  field bits<64> SoftFail = 0;
   let Size = 8;
 }
 
diff --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index 5e16061dc470f..209c3fae63f45 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -14,11 +14,6 @@ class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
     : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<16> Inst;
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<16> SoftFail = 0;
   let Size = 2;
 }
 
diff --git a/llvm/lib/Target/Sparc/SparcInstrFormats.td b/llvm/lib/Target/Sparc/SparcInstrFormats.td
index 79c4cb2128a0f..3d3dfdc52eb5d 100644
--- a/llvm/lib/Target/Sparc/SparcInstrFormats.td
+++ b/llvm/lib/Target/Sparc/SparcInstrFormats.td
@@ -23,7 +23,6 @@ class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
   let Pattern = pattern;
 
   let DecoderNamespace = "Sparc";
-  field bits<32> SoftFail = 0;
 
   let Itinerary = itin;
 }
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
index 3e9a515bf1153..d0a549518cc45 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -188,7 +188,6 @@ def getTwoOperandOpcode : InstrMapping {
 class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
 
   let Inst = op;
 }
@@ -196,7 +195,6 @@ class InstE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
 
   bits<8> I1;
 
@@ -207,7 +205,6 @@ class InstI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> I1;
   bits<4> I2;
@@ -221,7 +218,6 @@ class InstIE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> M1;
   bits<12> RI2;
@@ -236,7 +232,6 @@ class InstMII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<16> I2;
@@ -250,7 +245,6 @@ class InstRIa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<16> RI2;
@@ -264,7 +258,6 @@ class InstRIb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> M1;
   bits<16> RI2;
@@ -278,7 +271,6 @@ class InstRIc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<16> I2;
@@ -296,7 +288,6 @@ class InstRIEa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -315,7 +306,6 @@ class InstRIEb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<8> I2;
@@ -333,7 +323,6 @@ class InstRIEc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
@@ -350,7 +339,6 @@ class InstRIEd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIEe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
@@ -368,7 +356,6 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
                bits<8> I3Or = 0, bits<8> I4Or = 0>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -402,7 +389,6 @@ class InstRIEf<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern,
 class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> M3;
@@ -419,7 +405,6 @@ class InstRIEg<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<32> I2;
@@ -433,7 +418,6 @@ class InstRILa<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<32> RI2;
@@ -447,7 +431,6 @@ class InstRILb<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> M1;
   bits<32> RI2;
@@ -461,7 +444,6 @@ class InstRILc<bits<12> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<8> I2;
@@ -481,7 +463,6 @@ class InstRIS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<2, outs, ins, asmstr, pattern> {
   field bits<16> Inst;
-  field bits<16> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -494,7 +475,6 @@ class InstRR<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R3;
@@ -510,7 +490,6 @@ class InstRRD<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -524,7 +503,6 @@ class InstRRE<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -541,7 +519,6 @@ class InstRRFa<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -558,7 +535,6 @@ class InstRRFb<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -574,7 +550,6 @@ class InstRRFc<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -590,7 +565,6 @@ class InstRRFd<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -607,7 +581,6 @@ class InstRRFe<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<6, outs, ins, asmstr, pattern> {
   field bits<48> Inst;
-  field bits<48> SoftFail = 0;
 
   bits<4> R1;
   bits<4> R2;
@@ -628,7 +601,6 @@ class InstRRS<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : InstSystemZ<4, outs, ins, asmstr, pattern> {
   field bits<32> Inst;
-  field bits<32> SoftFail = 0;
 
   bits<4> R1;
   bits<4> X2;
@@ -647,7 +619,6 @@ class InstRXa<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
 class InstRXb<bits<8> op, dag outs, dag ins, string asmstr, list<d...
[truncated]

llvm-ci · 2025-08-21T02:48:58Z

LLVM Buildbot has detected a new failure on builder clang-armv8-quick running on linaro-clang-armv8-quick while building llvm at step 5 "ninja check 1".

Full details are available at: https://lab.llvm.org/buildbot/#/builders/154/builds/20504

Here is the relevant piece of the build log for the reference

Step 5 (ninja check 1) failure: stage 1 checked (failure)
******************** TEST 'Clangd Unit Tests :: ./ClangdTests/243/332' FAILED ********************
Script(shard):
--
GTEST_OUTPUT=json:/home/tcwg-buildbot/worker/clang-armv8-quick/stage1/tools/clang/tools/extra/clangd/unittests/./ClangdTests-Clangd Unit Tests-338005-243-332.json GTEST_SHUFFLE=0 GTEST_TOTAL_SHARDS=332 GTEST_SHARD_INDEX=243 /home/tcwg-buildbot/worker/clang-armv8-quick/stage1/tools/clang/tools/extra/clangd/unittests/./ClangdTests
--

Note: This is test shard 244 of 332.
[==========] Running 4 tests from 4 test suites.
[----------] Global test environment set-up.
[----------] 1 test from CompletionStringTest
[ RUN      ] CompletionStringTest.DocumentationWithAnnotation
[       OK ] CompletionStringTest.DocumentationWithAnnotation (54 ms)
[----------] 1 test from CompletionStringTest (54 ms total)

[----------] 1 test from FuzzyMatch
[ RUN      ] FuzzyMatch.Ranking
[       OK ] FuzzyMatch.Ranking (29 ms)
[----------] 1 test from FuzzyMatch (29 ms total)

[----------] 1 test from CrossFileRenameTests
[ RUN      ] CrossFileRenameTests.WithUpToDateIndex
ASTWorker building file /clangd-test/foo.h version null with command 
[/clangd-test]
clang -xobjective-c++ /clangd-test/foo.h
Driver produced command: cc1 -cc1 -triple armv8a-unknown-linux-gnueabihf -fsyntax-only -disable-free -clear-ast-before-backend -main-file-name foo.h -mrelocation-model pic -pic-level 2 -pic-is-pie -mframe-pointer=all -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -target-cpu generic -target-feature +read-tp-tpidruro -target-feature +vfp2 -target-feature +vfp2sp -target-feature +vfp3 -target-feature +vfp3d16 -target-feature +vfp3d16sp -target-feature +vfp3sp -target-feature +fp16 -target-feature +vfp4 -target-feature +vfp4d16 -target-feature +vfp4d16sp -target-feature +vfp4sp -target-feature +fp-armv8 -target-feature +fp-armv8d16 -target-feature +fp-armv8d16sp -target-feature +fp-armv8sp -target-feature -fullfp16 -target-feature +fp64 -target-feature +d32 -target-feature +sha2 -target-feature +aes -target-feature -fp16fml -target-feature +neon -target-abi aapcs-linux -mfloat-abi hard -debugger-tuning=gdb -fdebug-compilation-dir=/clangd-test -fcoverage-compilation-dir=/clangd-test -resource-dir lib/clang/22 -internal-isystem lib/clang/22/include -internal-isystem /usr/local/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -fdeprecated-macro -ferror-limit 19 -fno-signed-char -fgnuc-version=4.2.1 -fskip-odr-check-in-gmf -fobjc-runtime=gcc -fobjc-encode-cxx-class-template-spec -fobjc-exceptions -fcxx-exceptions -fexceptions -no-round-trip-args -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -x objective-c++ /clangd-test/foo.h
Building first preamble for /clangd-test/foo.h version null
Built preamble of size 420708 for file /clangd-test/foo.h version null in 1.49 seconds
indexed preamble AST for /clangd-test/foo.h version null:
  symbol slab: 0 symbols, 68 bytes
  ref slab: 0 symbols, 0 refs, 72 bytes
  relations slab: 0 relations, 12 bytes
indexed file AST for /clangd-test/foo.h version null:
  symbol slab: 3 symbols, 4584 bytes
  ref slab: 3 symbols, 5 refs, 4232 bytes
  relations slab: 0 relations, 12 bytes
Build dynamic index for main-file symbols with estimated memory usage of 11148 bytes
ASTWorker building file /clangd-test/foo.cc version null with command 
[/clangd-test]
clang -xobjective-c++ /clangd-test/foo.cc
Driver produced command: cc1 -cc1 -triple armv8a-unknown-linux-gnueabihf -fsyntax-only -disable-free -clear-ast-before-backend -main-file-name foo.cc -mrelocation-model pic -pic-level 2 -pic-is-pie -mframe-pointer=all -fmath-errno -ffp-contract=on -fno-rounding-math -mconstructor-aliases -target-cpu generic -target-feature +read-tp-tpidruro -target-feature +vfp2 -target-feature +vfp2sp -target-feature +vfp3 -target-feature +vfp3d16 -target-feature +vfp3d16sp -target-feature +vfp3sp -target-feature +fp16 -target-feature +vfp4 -target-feature +vfp4d16 -target-feature +vfp4d16sp -target-feature +vfp4sp -target-feature +fp-armv8 -target-feature +fp-armv8d16 -target-feature +fp-armv8d16sp -target-feature +fp-armv8sp -target-feature -fullfp16 -target-feature +fp64 -target-feature +d32 -target-feature +sha2 -target-feature +aes -target-feature -fp16fml -target-feature +neon -target-abi aapcs-linux -mfloat-abi hard -debugger-tuning=gdb -fdebug-compilation-dir=/clangd-test -fcoverage-compilation-dir=/clangd-test -resource-dir lib/clang/22 -internal-isystem lib/clang/22/include -internal-isystem /usr/local/include -internal-externc-isystem /include -internal-externc-isystem /usr/include -fdeprecated-macro -ferror-limit 19 -fno-signed-char -fgnuc-version=4.2.1 -fskip-odr-check-in-gmf -fobjc-runtime=gcc -fobjc-encode-cxx-class-template-spec -fobjc-exceptions -fcxx-exceptions -fexceptions -no-round-trip-args -faddrsig -D__GCC_HAVE_DWARF2_CFI_ASM=1 -x objective-c++ /clangd-test/foo.cc
Building first preamble for /clangd-test/foo.cc version null
Built preamble of size 421652 for file /clangd-test/foo.cc version null in 0.16 seconds
indexed preamble AST for /clangd-test/foo.cc version null:
  symbol slab: 3 symbols, 4584 bytes
  ref slab: 0 symbols, 0 refs, 72 bytes
  relations slab: 0 relations, 12 bytes
Build dynamic index for header symbols with estimated memory usage of 6408 bytes
indexed file AST for /clangd-test/foo.cc version null:
  symbol slab: 3 symbols, 4584 bytes
  ref slab: 4 symbols, 9 refs, 4232 bytes
...

[Target] Remove SoftFail field on targets that don't use it

32c6570

That is, on all targets except ARM and AArch64. This field used to be required due to a bug, but it was fixed long ago by 23423c0.

s-barannikov requested review from arsenm, uweigand and topperc August 21, 2025 01:38

llvmbot added backend:AMDGPU backend:Hexagon backend:MIPS backend:MSP430 backend:RISC-V backend:PowerPC backend:Sparc backend:SystemZ backend:CSKY backend:ARC backend:loongarch backend:Xtensa backend:Lanai labels Aug 21, 2025

arsenm approved these changes Aug 21, 2025

View reviewed changes

s-barannikov merged commit d6679d5 into llvm:main Aug 21, 2025
23 checks passed

s-barannikov deleted the tablegen/decoder/redundant-softfail branch August 21, 2025 02:21

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[Target] Remove SoftFail field on targets that don't use it (NFC) #154659

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[Target] Remove SoftFail field on targets that don't use it (NFC) #154659

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