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[RISCV][POC] Should we be using ADD for disjoint or? #155669

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[RISCV][POC] Should we be using ADD for disjoint or? #155669

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5 changes: 3 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfo.td
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Expand Up @@ -1465,11 +1465,12 @@ def : PatGprUimmLog2XLen<shl, SLLI>;
def : PatGprUimmLog2XLen<srl, SRLI>;
def : PatGprUimmLog2XLen<sra, SRAI>;

// Select 'or' as ADDI if the immediate bits are known to be 0 in $rs1. This
// can improve compressibility.
def riscv_or_disjoint : PatFrag<(ops node:$lhs, node:$rhs), (or node:$lhs, node:$rhs),[{
return orDisjoint(N);
}]>;
// Select 'or' as ADD or ADDI if known disjoint. There is no c.ori, and c.add allows
// more registers than c.or.
def : PatGprGpr<riscv_or_disjoint, ADD>;
def : PatGprSimm12<riscv_or_disjoint, ADDI>;

def add_like : PatFrags<(ops node:$lhs, node:$rhs),
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18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/add-before-shl.ll
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Expand Up @@ -172,14 +172,14 @@ define i128 @add_wide_operand(i128 %a) nounwind {
; RV32I-NEXT: srli a5, a2, 29
; RV32I-NEXT: slli a6, a3, 3
; RV32I-NEXT: srli a3, a3, 29
; RV32I-NEXT: or a5, a6, a5
; RV32I-NEXT: add a5, a6, a5
; RV32I-NEXT: slli a6, a4, 3
; RV32I-NEXT: or a3, a6, a3
; RV32I-NEXT: add a3, a6, a3
; RV32I-NEXT: lui a6, 128
; RV32I-NEXT: srli a4, a4, 29
; RV32I-NEXT: slli a1, a1, 3
; RV32I-NEXT: slli a2, a2, 3
; RV32I-NEXT: or a1, a1, a4
; RV32I-NEXT: add a1, a1, a4
; RV32I-NEXT: add a1, a1, a6
; RV32I-NEXT: sw a2, 0(a0)
; RV32I-NEXT: sw a5, 4(a0)
Expand All @@ -192,7 +192,7 @@ define i128 @add_wide_operand(i128 %a) nounwind {
; RV64I-NEXT: srli a2, a0, 61
; RV64I-NEXT: slli a1, a1, 3
; RV64I-NEXT: slli a0, a0, 3
; RV64I-NEXT: or a1, a1, a2
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: slli a2, a2, 51
; RV64I-NEXT: add a1, a1, a2
Expand All @@ -208,26 +208,26 @@ define i128 @add_wide_operand(i128 %a) nounwind {
; RV32C-NEXT: add a6, a4, a5
; RV32C-NEXT: srli a5, a2, 29
; RV32C-NEXT: slli a4, a3, 3
; RV32C-NEXT: c.or a4, a5
; RV32C-NEXT: c.add a4, a5
; RV32C-NEXT: srli a5, a1, 29
; RV32C-NEXT: c.srli a3, 29
; RV32C-NEXT: c.slli a1, 3
; RV32C-NEXT: c.slli a2, 3
; RV32C-NEXT: c.slli a6, 3
; RV32C-NEXT: c.or a1, a3
; RV32C-NEXT: or a3, a6, a5
; RV32C-NEXT: c.add a1, a3
; RV32C-NEXT: c.add a5, a6
; RV32C-NEXT: c.sw a2, 0(a0)
; RV32C-NEXT: c.sw a4, 4(a0)
; RV32C-NEXT: c.sw a1, 8(a0)
; RV32C-NEXT: c.sw a3, 12(a0)
; RV32C-NEXT: c.sw a5, 12(a0)
; RV32C-NEXT: c.jr ra
;
; RV64C-LABEL: add_wide_operand:
; RV64C: # %bb.0:
; RV64C-NEXT: srli a2, a0, 61
; RV64C-NEXT: c.slli a1, 3
; RV64C-NEXT: c.slli a0, 3
; RV64C-NEXT: c.or a1, a2
; RV64C-NEXT: c.add a1, a2
; RV64C-NEXT: c.li a2, 1
; RV64C-NEXT: c.slli a2, 51
; RV64C-NEXT: c.add a1, a2
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/addcarry.ll
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Expand Up @@ -32,13 +32,13 @@ define i64 @addcarry(i64 %x, i64 %y) nounwind {
; RISCV32-NEXT: # %bb.3:
; RISCV32-NEXT: sub a5, a5, a0
; RISCV32-NEXT: .LBB0_4:
; RISCV32-NEXT: slli a5, a5, 30
; RISCV32-NEXT: srli a1, a4, 2
; RISCV32-NEXT: slli a1, a5, 30
; RISCV32-NEXT: srli a3, a4, 2
; RISCV32-NEXT: slli a4, a4, 30
; RISCV32-NEXT: mul a0, a0, a2
; RISCV32-NEXT: or a1, a5, a1
; RISCV32-NEXT: add a1, a1, a3
; RISCV32-NEXT: srli a0, a0, 2
; RISCV32-NEXT: or a0, a4, a0
; RISCV32-NEXT: add a0, a4, a0
; RISCV32-NEXT: ret
%tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2);
ret i64 %tmp;
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/alu64.ll
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Expand Up @@ -120,7 +120,7 @@ define i64 @slli(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: srli a2, a0, 25
; RV32I-NEXT: slli a1, a1, 7
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: add a1, a1, a2
; RV32I-NEXT: slli a0, a0, 7
; RV32I-NEXT: ret
%1 = shl i64 %a, 7
Expand All @@ -137,7 +137,7 @@ define i64 @srli(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a1, 24
; RV32I-NEXT: srli a0, a0, 8
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: srli a1, a1, 8
; RV32I-NEXT: ret
%1 = lshr i64 %a, 8
Expand All @@ -154,7 +154,7 @@ define i64 @srai(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: slli a2, a1, 23
; RV32I-NEXT: srli a0, a0, 9
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: add a0, a0, a2
; RV32I-NEXT: srai a1, a1, 9
; RV32I-NEXT: ret
%1 = ashr i64 %a, 9
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2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/and-negpow2-cmp.ll
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Expand Up @@ -8,7 +8,7 @@ define i1 @test1(i64 %x) {
; RV32-NEXT: slli a2, a1, 2
; RV32-NEXT: srli a0, a0, 30
; RV32-NEXT: srai a1, a1, 30
; RV32-NEXT: or a0, a0, a2
; RV32-NEXT: add a0, a0, a2
; RV32-NEXT: xori a0, a0, -2
; RV32-NEXT: not a1, a1
; RV32-NEXT: or a0, a0, a1
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/avgceils.ll
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Expand Up @@ -189,7 +189,7 @@ define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {
; RV32I-NEXT: slli a1, a1, 31
; RV32I-NEXT: srli a3, a3, 1
; RV32I-NEXT: sub a4, a4, a2
; RV32I-NEXT: or a3, a3, a1
; RV32I-NEXT: add a3, a3, a1
; RV32I-NEXT: sltu a1, a0, a3
; RV32I-NEXT: sub a1, a4, a1
; RV32I-NEXT: sub a0, a0, a3
Expand Down Expand Up @@ -220,7 +220,7 @@ define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind {
; RV32I-NEXT: slli a1, a1, 31
; RV32I-NEXT: srli a3, a3, 1
; RV32I-NEXT: sub a4, a4, a2
; RV32I-NEXT: or a3, a3, a1
; RV32I-NEXT: add a3, a3, a1
; RV32I-NEXT: sltu a1, a0, a3
; RV32I-NEXT: sub a1, a4, a1
; RV32I-NEXT: sub a0, a0, a3
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/avgceilu.ll
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Expand Up @@ -185,7 +185,7 @@ define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {
; RV32I-NEXT: slli a1, a1, 31
; RV32I-NEXT: srli a3, a3, 1
; RV32I-NEXT: sub a4, a4, a2
; RV32I-NEXT: or a3, a3, a1
; RV32I-NEXT: add a3, a3, a1
; RV32I-NEXT: sltu a1, a0, a3
; RV32I-NEXT: sub a1, a4, a1
; RV32I-NEXT: sub a0, a0, a3
Expand Down Expand Up @@ -216,7 +216,7 @@ define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind {
; RV32I-NEXT: slli a1, a1, 31
; RV32I-NEXT: srli a3, a3, 1
; RV32I-NEXT: sub a4, a4, a2
; RV32I-NEXT: or a3, a3, a1
; RV32I-NEXT: add a3, a3, a1
; RV32I-NEXT: sltu a1, a0, a3
; RV32I-NEXT: sub a1, a4, a1
; RV32I-NEXT: sub a0, a0, a3
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/avgfloors.ll
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Expand Up @@ -175,7 +175,7 @@ define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {
; RV32I-NEXT: xor a4, a0, a2
; RV32I-NEXT: slli a1, a1, 31
; RV32I-NEXT: srli a4, a4, 1
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: add a1, a4, a1
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: add a0, a2, a1
; RV32I-NEXT: sltu a1, a0, a2
Expand Down Expand Up @@ -206,7 +206,7 @@ define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind {
; RV32I-NEXT: xor a4, a0, a2
; RV32I-NEXT: slli a1, a1, 31
; RV32I-NEXT: srli a4, a4, 1
; RV32I-NEXT: or a1, a4, a1
; RV32I-NEXT: add a1, a4, a1
; RV32I-NEXT: and a2, a0, a2
; RV32I-NEXT: add a0, a2, a1
; RV32I-NEXT: sltu a1, a0, a2
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/avgflooru.ll
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Expand Up @@ -176,8 +176,8 @@ define i64 @test_fixed_i64(i64 %a0, i64 %a1) nounwind {
; RV32I-NEXT: srli a3, a1, 1
; RV32I-NEXT: slli a4, a1, 31
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: or a1, a3, a2
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: add a1, a3, a2
; RV32I-NEXT: add a0, a0, a4
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_fixed_i64:
Expand Down Expand Up @@ -209,8 +209,8 @@ define i64 @test_ext_i64(i64 %a0, i64 %a1) nounwind {
; RV32I-NEXT: srli a3, a1, 1
; RV32I-NEXT: slli a4, a1, 31
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: or a1, a3, a2
; RV32I-NEXT: or a0, a0, a4
; RV32I-NEXT: add a1, a3, a2
; RV32I-NEXT: add a0, a0, a4
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_ext_i64:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/bfloat-arith.ll
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Expand Up @@ -79,7 +79,7 @@ define bfloat @fsgnj_bf16(bfloat %a, bfloat %b) nounwind {
; RV32IZFBFMIN-NEXT: fmv.x.h a1, fa0
; RV32IZFBFMIN-NEXT: slli a1, a1, 17
; RV32IZFBFMIN-NEXT: srli a1, a1, 17
; RV32IZFBFMIN-NEXT: or a0, a1, a0
; RV32IZFBFMIN-NEXT: add a0, a1, a0
; RV32IZFBFMIN-NEXT: fmv.h.x fa0, a0
; RV32IZFBFMIN-NEXT: ret
;
Expand All @@ -91,7 +91,7 @@ define bfloat @fsgnj_bf16(bfloat %a, bfloat %b) nounwind {
; RV64IZFBFMIN-NEXT: fmv.x.h a1, fa0
; RV64IZFBFMIN-NEXT: slli a1, a1, 49
; RV64IZFBFMIN-NEXT: srli a1, a1, 49
; RV64IZFBFMIN-NEXT: or a0, a1, a0
; RV64IZFBFMIN-NEXT: add a0, a1, a0
; RV64IZFBFMIN-NEXT: fmv.h.x fa0, a0
; RV64IZFBFMIN-NEXT: ret
%1 = call bfloat @llvm.copysign.bf16(bfloat %a, bfloat %b)
Expand Down Expand Up @@ -133,7 +133,7 @@ define bfloat @fsgnjn_bf16(bfloat %a, bfloat %b) nounwind {
; RV32IZFBFMIN-NEXT: fmv.x.h a1, fa0
; RV32IZFBFMIN-NEXT: slli a1, a1, 17
; RV32IZFBFMIN-NEXT: srli a1, a1, 17
; RV32IZFBFMIN-NEXT: or a0, a1, a0
; RV32IZFBFMIN-NEXT: add a0, a1, a0
; RV32IZFBFMIN-NEXT: fmv.h.x fa0, a0
; RV32IZFBFMIN-NEXT: ret
;
Expand All @@ -150,7 +150,7 @@ define bfloat @fsgnjn_bf16(bfloat %a, bfloat %b) nounwind {
; RV64IZFBFMIN-NEXT: fmv.x.h a1, fa0
; RV64IZFBFMIN-NEXT: slli a1, a1, 49
; RV64IZFBFMIN-NEXT: srli a1, a1, 49
; RV64IZFBFMIN-NEXT: or a0, a1, a0
; RV64IZFBFMIN-NEXT: add a0, a1, a0
; RV64IZFBFMIN-NEXT: fmv.h.x fa0, a0
; RV64IZFBFMIN-NEXT: ret
%1 = fadd bfloat %a, %b
Expand Down
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