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[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default #155693

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Merged
merged 1 commit into from
Aug 27, 2025
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[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default #155693

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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
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Expand Up @@ -966,17 +966,17 @@ bool RISCVRegisterInfo::getRegAllocationHints(
}
}

// Add a hint if it would allow auipc/lui+addi(w) fusion.
// Add a hint if it would allow auipc/lui+addi(w) fusion. We do this even
// without the fusions explicitly enabled as the impact is rarely negative
// and some cores do implement this fusion.
if ((MI.getOpcode() == RISCV::ADDIW || MI.getOpcode() == RISCV::ADDI) &&
MI.getOperand(1).isReg()) {
const MachineBasicBlock &MBB = *MI.getParent();
MachineBasicBlock::const_iterator I = MI.getIterator();
// Is the previous instruction a LUI or AUIPC that can be fused?
if (I != MBB.begin()) {
I = skipDebugInstructionsBackward(std::prev(I), MBB.begin());
if (((I->getOpcode() == RISCV::LUI && Subtarget.hasLUIADDIFusion()) ||
(I->getOpcode() == RISCV::AUIPC &&
Subtarget.hasAUIPCADDIFusion())) &&
if ((I->getOpcode() == RISCV::LUI || I->getOpcode() == RISCV::AUIPC) &&
I->getOperand(0).getReg() == MI.getOperand(1).getReg()) {
if (OpIdx == 0)
tryAddHint(MO, MI.getOperand(1), /*NeedGPRC=*/false);
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/GlobalISel/vararg.ll
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Expand Up @@ -1155,8 +1155,8 @@ define void @va3_caller() nounwind {
; RV32: # %bb.0:
; RV32-NEXT: addi sp, sp, -16
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: lui a0, 5
; RV32-NEXT: addi a3, a0, -480
; RV32-NEXT: lui a3, 5
; RV32-NEXT: addi a3, a3, -480
; RV32-NEXT: li a0, 2
; RV32-NEXT: li a1, 1111
; RV32-NEXT: li a2, 0
Expand Down Expand Up @@ -1184,8 +1184,8 @@ define void @va3_caller() nounwind {
; RV32-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32-WITHFP-NEXT: addi s0, sp, 16
; RV32-WITHFP-NEXT: lui a0, 5
; RV32-WITHFP-NEXT: addi a3, a0, -480
; RV32-WITHFP-NEXT: lui a3, 5
; RV32-WITHFP-NEXT: addi a3, a3, -480
; RV32-WITHFP-NEXT: li a0, 2
; RV32-WITHFP-NEXT: li a1, 1111
; RV32-WITHFP-NEXT: li a2, 0
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
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Expand Up @@ -393,8 +393,8 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: # %bb.1: # %cond.false
; RV32I-NEXT: neg a1, a0
; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: lui a2, 30667
; RV32I-NEXT: addi s2, a2, 1329
; RV32I-NEXT: lui s2, 30667
; RV32I-NEXT: addi s2, s2, 1329
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, s2
Expand Down Expand Up @@ -460,8 +460,8 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32M-NEXT: or a2, a0, a1
; RV32M-NEXT: beqz a2, .LBB3_3
; RV32M-NEXT: # %bb.1: # %cond.false
; RV32M-NEXT: lui a2, 30667
; RV32M-NEXT: addi a3, a2, 1329
; RV32M-NEXT: lui a3, 30667
; RV32M-NEXT: addi a3, a3, 1329
; RV32M-NEXT: lui a2, %hi(.LCPI3_0)
; RV32M-NEXT: addi a2, a2, %lo(.LCPI3_0)
; RV32M-NEXT: bnez a0, .LBB3_4
Expand Down Expand Up @@ -847,8 +847,8 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: and a0, s2, a0
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi s3, a1, 1329
; RV32I-NEXT: lui s3, 30667
; RV32I-NEXT: addi s3, s3, 1329
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s0, a0
Expand Down Expand Up @@ -900,8 +900,8 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
;
; RV32M-LABEL: test_cttz_i64_zero_undef:
; RV32M: # %bb.0:
; RV32M-NEXT: lui a2, 30667
; RV32M-NEXT: addi a3, a2, 1329
; RV32M-NEXT: lui a3, 30667
; RV32M-NEXT: addi a3, a3, 1329
; RV32M-NEXT: lui a2, %hi(.LCPI7_0)
; RV32M-NEXT: addi a2, a2, %lo(.LCPI7_0)
; RV32M-NEXT: bnez a0, .LBB7_2
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
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Expand Up @@ -43,8 +43,8 @@ define signext i32 @ctz_dereferencing_pointer(ptr %b) nounwind {
; RV32I-NEXT: lw s4, 4(a0)
; RV32I-NEXT: neg a0, s2
; RV32I-NEXT: and a0, s2, a0
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi s1, a1, 1329
; RV32I-NEXT: lui s1, 30667
; RV32I-NEXT: addi s1, s1, 1329
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s0, a0
Expand Down Expand Up @@ -563,8 +563,8 @@ define signext i32 @ctz4(i64 %b) nounwind {
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: neg a0, a0
; RV32I-NEXT: and a0, s0, a0
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi s3, a1, 1329
; RV32I-NEXT: lui s3, 30667
; RV32I-NEXT: addi s3, s3, 1329
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s1, a0
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Expand Up @@ -1691,9 +1691,8 @@ define signext i16 @fcvt_w_s_sat_i16(double %a) nounwind {
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a1
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 265728
; RV32I-NEXT: addi a3, a0, -64
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lui a3, 265728
; RV32I-NEXT: addi a3, a3, -64
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: call __gtdf2
; RV32I-NEXT: mv s2, a0
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/float-convert.ll
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Expand Up @@ -1474,8 +1474,8 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s1, 1048568
; RV32I-NEXT: .LBB24_2: # %start
; RV32I-NEXT: lui a0, 290816
; RV32I-NEXT: addi a1, a0, -512
; RV32I-NEXT: lui a1, 290816
; RV32I-NEXT: addi a1, a1, -512
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2
; RV32I-NEXT: blez a0, .LBB24_4
Expand Down Expand Up @@ -1516,8 +1516,8 @@ define signext i16 @fcvt_w_s_sat_i16(float %a) nounwind {
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: lui s1, 1048568
; RV64I-NEXT: .LBB24_2: # %start
; RV64I-NEXT: lui a0, 290816
; RV64I-NEXT: addi a1, a0, -512
; RV64I-NEXT: lui a1, 290816
; RV64I-NEXT: addi a1, a1, -512
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB24_4
Expand Down Expand Up @@ -1640,8 +1640,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __fixunssfsi
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 292864
; RV32I-NEXT: addi a1, a0, -256
; RV32I-NEXT: lui a1, 292864
; RV32I-NEXT: addi a1, a1, -256
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __gtsf2
; RV32I-NEXT: lui a1, 16
Expand Down Expand Up @@ -1677,8 +1677,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(float %a) nounwind {
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __fixunssfdi
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 292864
; RV64I-NEXT: addi a1, a0, -256
; RV64I-NEXT: lui a1, 292864
; RV64I-NEXT: addi a1, a1, -256
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: lui a1, 16
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/half-convert.ll
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Expand Up @@ -328,8 +328,8 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s1, 1048568
; RV32I-NEXT: .LBB1_2: # %start
; RV32I-NEXT: lui a0, 290816
; RV32I-NEXT: addi a1, a0, -512
; RV32I-NEXT: lui a1, 290816
; RV32I-NEXT: addi a1, a1, -512
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2
; RV32I-NEXT: blez a0, .LBB1_4
Expand Down Expand Up @@ -371,8 +371,8 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: lui s1, 1048568
; RV64I-NEXT: .LBB1_2: # %start
; RV64I-NEXT: lui a0, 290816
; RV64I-NEXT: addi a1, a0, -512
; RV64I-NEXT: lui a1, 290816
; RV64I-NEXT: addi a1, a1, -512
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB1_4
Expand Down Expand Up @@ -812,8 +812,8 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: lui a0, 292864
; RV32I-NEXT: addi a1, a0, -256
; RV32I-NEXT: lui a1, 292864
; RV32I-NEXT: addi a1, a1, -256
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: call __gtsf2
; RV32I-NEXT: bgtz a0, .LBB3_2
Expand Down Expand Up @@ -850,8 +850,8 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gesf2
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: lui a0, 292864
; RV64I-NEXT: addi a1, a0, -256
; RV64I-NEXT: lui a1, 292864
; RV64I-NEXT: addi a1, a1, -256
; RV64I-NEXT: mv a0, s3
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: bgtz a0, .LBB3_2
Expand Down Expand Up @@ -6416,8 +6416,8 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: lui s1, 1048568
; RV32I-NEXT: .LBB32_2: # %start
; RV32I-NEXT: lui a0, 290816
; RV32I-NEXT: addi a1, a0, -512
; RV32I-NEXT: lui a1, 290816
; RV32I-NEXT: addi a1, a1, -512
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2
; RV32I-NEXT: blez a0, .LBB32_4
Expand Down Expand Up @@ -6461,8 +6461,8 @@ define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: lui s1, 1048568
; RV64I-NEXT: .LBB32_2: # %start
; RV64I-NEXT: lui a0, 290816
; RV64I-NEXT: addi a1, a0, -512
; RV64I-NEXT: lui a1, 290816
; RV64I-NEXT: addi a1, a1, -512
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB32_4
Expand Down Expand Up @@ -6903,8 +6903,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, 292864
; RV32I-NEXT: addi a1, a0, -256
; RV32I-NEXT: lui a1, 292864
; RV32I-NEXT: addi a1, a1, -256
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __gtsf2
; RV32I-NEXT: blez a0, .LBB34_2
Expand Down Expand Up @@ -6944,8 +6944,8 @@ define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gesf2
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: lui a0, 292864
; RV64I-NEXT: addi a1, a0, -256
; RV64I-NEXT: lui a1, 292864
; RV64I-NEXT: addi a1, a1, -256
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __gtsf2
; RV64I-NEXT: blez a0, .LBB34_2
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/imm.ll
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Expand Up @@ -837,8 +837,8 @@ define i64 @imm64_5() nounwind {
define i64 @imm64_6() nounwind {
; RV32I-LABEL: imm64_6:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 74565
; RV32I-NEXT: addi a1, a0, 1656
; RV32I-NEXT: lui a1, 74565
; RV32I-NEXT: addi a1, a1, 1656
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -3895,8 +3895,8 @@ define i64 @imm_neg_10307948543() {
define i64 @li_rori_1() {
; RV32I-LABEL: li_rori_1:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a0, 1048567
; RV32I-NEXT: addi a1, a0, 2047
; RV32I-NEXT: lui a1, 1048567
; RV32I-NEXT: addi a1, a1, 2047
; RV32I-NEXT: li a0, -1
; RV32I-NEXT: ret
;
Expand Down
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