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[M68k] Fix register class of index operands #156146
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Index operands can only be DR registers.
@llvm/pr-subscribers-backend-m68k Author: Sergei Barannikov (s-barannikov) ChangesIndex operands can only be DR registers. Full diff: https://github.com/llvm/llvm-project/pull/156146.diff 1 Files Affected:
diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.td b/llvm/lib/Target/M68k/M68kInstrInfo.td
index 1200c493f9fca..fe839015eaf67 100644
--- a/llvm/lib/Target/M68k/M68kInstrInfo.td
+++ b/llvm/lib/Target/M68k/M68kInstrInfo.td
@@ -344,8 +344,8 @@ foreach size = ["8", "16", "32"] in {
def MxARII : MxOpClass<"ARII">;
foreach size = ["8", "16", "32"] in {
defvar ResSize = !cast<MxSize>("MxSize"#size);
- def MxARII # size : MxMemOp<(ops i8imm:$disp, AR32:$reg, XR32:$index), ResSize, "f", "printARII"#size#"Mem", MxARII>;
- def MxARII # size # _TC : MxMemOp<(ops i8imm:$disp, AR32_TC:$reg, XR32:$index), ResSize, "f", "printARII"#size#"Mem", MxARII>;
+ def MxARII # size : MxMemOp<(ops i8imm:$disp, AR32:$reg, DR32:$index), ResSize, "f", "printARII"#size#"Mem", MxARII>;
+ def MxARII # size # _TC : MxMemOp<(ops i8imm:$disp, AR32_TC:$reg, DR32:$index), ResSize, "f", "printARII"#size#"Mem", MxARII>;
} // foreach size
// ABSOLUTE SHORT ADDRESS. This addressing mode requires one word of extension.
@@ -394,7 +394,7 @@ def MxPCD # size : MxMemOp<(ops i16imm), ResSize, "q", "printPCD"#size#"Mem", M
// word, and the contents of the index register. The value in the program
// counter is the address of the extension word. This reference is classified as
// a program reference.
-def MxPCI # size : MxMemOp<(ops i8imm:$disp, XR32:$index), ResSize, "k", "printPCI"#size#"Mem", MxPCI>;
+def MxPCI # size : MxMemOp<(ops i8imm:$disp, DR32:$index), ResSize, "k", "printPCI"#size#"Mem", MxPCI>;
} // foreach size
} // OPERAND_PCREL
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I couldn't figure out how to test this. I discovered this issue when working on TableGen disassembler backend. |
OK I've figured out what the real issue is, but it is over my head to fix it right now.
Here, Other conflicts are similar, some are more involved. Full list of conflicts
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Index operands can only be DR registers.