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[AMDGPU] SIFoldOperands check that shrunk op is valid #156298

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[AMDGPU] SIFoldOperands check that shrunk op is valid #156298

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28cc8d8
[AMDGPU] Pre-commit test for folding abs64 error
dstutt Sep 1, 2025
f6e09b8
[AMDGPU] SIFoldOperands check that shrunk op is valid
dstutt Aug 28, 2025
78798d4
Fix test
dstutt Sep 2, 2025
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2 changes: 2 additions & 0 deletions llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -868,6 +868,8 @@ bool SIFoldOperandsImpl::tryAddToFoldList(
// Make sure to get the 32-bit version of the commuted opcode.
unsigned MaybeCommutedOpc = MI->getOpcode();
Op32 = AMDGPU::getVOPe32(MaybeCommutedOpc);
if (TII->pseudoToMCOpcode(Op32) == -1)
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SIInstrInfo::commuteOpcode already checks this, is this being skipped somehow?

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I think the difference here is that it is trying to find the VOPe32 variant - which might not exist, even if the commuteOpcode did. (Part of the shrink).

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I think this check should be pulled into a helper function in SIInstrInfo instead of directly using pseudoToMCOpcode. We already have hasVALU32BitEncoding, but it returns a bool instead of the new opcode. Can you generalize that to return the shrunk opcode if valid?

return false;
}

appendFoldCandidate(FoldList, MI, CommuteOpNo, OpToFold, /*Commuted=*/true,
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39 changes: 39 additions & 0 deletions llvm/test/CodeGen/AMDGPU/fold-abs64.mir
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@@ -0,0 +1,39 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=si-fold-operands %s -o - | FileCheck %s

--- |
@sym = external constant i32
define void @fn() { ret void }
define void @fn2() { ret void }
...

---
name: fn
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: fn
; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-abs64) @sym
; CHECK-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 undef [[DEF]].sub0, undef [[S_MOV_B64_]].sub0, 0, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]
%0:vreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64 target-flags(amdgpu-abs64) @sym
%2:vgpr_32, %3:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 undef %1.sub0, undef %0.sub0, 0, implicit $exec
S_ENDPGM 0, implicit %2
...

---
name: fn2
tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: fn2
; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
; CHECK-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 591751049, undef [[DEF]].sub0, 0, implicit $exec
; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]
%0:vreg_64 = IMPLICIT_DEF
%1:sreg_64 = S_MOV_B64 4886718345
%2:vgpr_32, %3:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 undef %1.sub0, undef %0.sub0, 0, implicit $exec
S_ENDPGM 0, implicit %2
...
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