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[RISCV] Fix shift instruction opcodes in getArithmeticInstrCost #156335

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[RISCV] Fix shift instruction opcodes in getArithmeticInstrCost #156335

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2cd3a56
[RISCV] Fix multiple instruction mapping errors in TTI
steven-studio Sep 1, 2025
acb4ab0
Merge remote-tracking branch 'upstream/main'
steven-studio Sep 1, 2025
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12 changes: 12 additions & 0 deletions llvm/lib/Target/RISCV/RISCVGISel.td
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Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,18 @@
include "RISCV.td"
include "RISCVCombine.td"

// (setult reg, imm12) → SLTIU
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What is this change?

def : Pat<(XLenVT (setult (XLenVT GPR:$rs1), simm12:$imm)),
(SLTIU GPR:$rs1, simm12:$imm)>;

let Predicates = [HasStdExtZbb, IsRV64] in {
def : Pat<(i64 (sext (i16 GPR:$rs))), (SEXT_H GPR:$rs)>;
def : Pat<(i64 (zext (i16 GPR:$rs))), (ZEXT_H_RV64 GPR:$rs)>;
}
let Predicates = [HasStdExtZbb, IsRV32] in {
def : Pat<(i32 (zext (i16 GPR:$rs))), (ZEXT_H_RV32 GPR:$rs)>;
}

def simm12Plus1 : ImmLeaf<XLenVT, [{
return (isInt<12>(Imm) && Imm != -2048) || Imm == 2048;}]>;
def simm12Plus1i32 : ImmLeaf<i32, [{
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16 changes: 10 additions & 6 deletions llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
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Expand Up @@ -85,14 +85,14 @@ RISCVTTIImpl::getRISCVInstructionCost(ArrayRef<unsigned> OpCodes, MVT VT,
case RISCV::VFREDUSUM_VS: {
unsigned VL = VT.getVectorMinNumElements();
if (!VT.isFixedLengthVector())
VL *= *getVScaleForTuning();
VL *= getVScaleForTuning().value_or(1);
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This change isn't mentioned in the description?

Cost += Log2_32_Ceil(VL);
break;
}
case RISCV::VFREDOSUM_VS: {
unsigned VL = VT.getVectorMinNumElements();
if (!VT.isFixedLengthVector())
VL *= *getVScaleForTuning();
VL *= getVScaleForTuning().value_or(1);
Cost += VL;
break;
}
Expand Down Expand Up @@ -242,7 +242,7 @@ InstructionCost RISCVTTIImpl::getIntImmCostInst(unsigned Opcode, unsigned Idx,
// One more or less than a power of 2 can use SLLI+ADD/SUB.
if ((Imm + 1).isPowerOf2() || (Imm - 1).isPowerOf2())
return TTI::TCC_Free;
// FIXME: There is no MULI instruction.
// No MULI in RISC-V, but 12-bit immediates can still be used in sequences.
Takes12BitImm = true;
break;
case Instruction::Sub:
Expand Down Expand Up @@ -1342,7 +1342,7 @@ RISCVTTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
Op = RISCV::VSADD_VV;
break;
case Intrinsic::ssub_sat:
Op = RISCV::VSSUBU_VV;
Op = RISCV::VSSUB_VV;
break;
case Intrinsic::uadd_sat:
Op = RISCV::VSADDU_VV;
Expand Down Expand Up @@ -1766,7 +1766,7 @@ unsigned RISCVTTIImpl::getEstimatedVLFor(VectorType *Ty) const {
if (isa<ScalableVectorType>(Ty)) {
const unsigned EltSize = DL.getTypeSizeInBits(Ty->getElementType());
const unsigned MinSize = DL.getTypeSizeInBits(Ty).getKnownMinValue();
const unsigned VectorBits = *getVScaleForTuning() * RISCV::RVVBitsPerBlock;
const unsigned VectorBits = getVScaleForTuning().value_or(1) * RISCV::RVVBitsPerBlock;
return RISCVTargetLowering::computeVLMAX(VectorBits, EltSize, MinSize);
}
return cast<FixedVectorType>(Ty)->getNumElements();
Expand Down Expand Up @@ -2510,9 +2510,13 @@ InstructionCost RISCVTTIImpl::getArithmeticInstrCost(
Op = RISCV::VADD_VV;
break;
case ISD::SHL:
Op = RISCV::VSLL_VV;
break;
case ISD::SRL:
Op = RISCV::VSRL_VV;
break;
case ISD::SRA:
Op = RISCV::VSLL_VV;
Op = RISCV::VSRA_VV;
break;
case ISD::AND:
case ISD::OR:
Expand Down