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[llvm-exegesis] [AArch64] Reland Resolving "not all operands are initialized by snippet generator" #156423
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[llvm-exegesis] [AArch64] Reland Resolving "not all operands are initialized by snippet generator" #156423
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… by the snippet generator" by omit OPERAND_UNKNOWN to Immediate
…nippet generation, omiting immediate valued 0.
…r omitted opcode type.
…move out of scope operand type.
…ndomizeTargetMCOperand to omit to Immediate
… omittion to resolve illegal instruction
… error-resolution.s
…d type in randomizeTargetMCOperand
… MSL immediate operands for 32-bit SIMD constants
… value handling for MOVIv2s_msl
…_TYPES i.e. OPERAND_MSL_SHIFT_4S and OPERAND_MSL_SHIFT_2S
… handling and testcase
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LGTM, assuming you've rerun the test quite a few times locally to ensure there aren't any flakes.
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// Hacky temporary fix works by defaulting all OPERAND_UNKNOWN to | ||
// immediate value 0, but this introduce illegal instruction error for below | ||
// system instructions will need to be omitted with OperandType or opcode |
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nit:
but this introduces illegal instruction error for the below instructions.
System instructions ...
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Updated the comment. Thanks!
// - Type 8: imm at [23:16], [55:48], shift = 272 (0x110) → msl #16 | ||
// Corresponds AArch64_AM::encodeAdvSIMDModImmType7() | ||
// But, v2s_msl and v4s_msl instructions accept either form, | ||
// Thus, Arbitrarily chosing 264 (msl #8) for simplicity. |
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Should we also count for 272 ? We may not want to enforce 264 always?
Edit: This can be extended for other imm operands which are defaulted to some value, probably in a separate patch- essentially "taking value as an arg" . @boomanaiden154 @sjoerdmeijer @davemgreen what do you think?
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Agree, this area needs some work in follow ups, but let's start somewhere with this, so is okay as a start.
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LGTM otherwise!
…ing OPERAND_UNKNOWN
Reland #142529 (Resolving "not all operands are initialized by snippet generator")
Introduced changes in implementation of
randomizeTargetMCOperand()
for AArch64 that omittingOPERAND_SHIFT_MSL
,OPERAND_PCREL
to an immediate value of 264 and 8 respectively.PS: Omitting
MCOI::OPERAND_FIRST_TARGET/llvm:AArch64:OPERAND_IMPLICIT_IMM_0
similarly, to value 0. It was low hanging change thus added in this PR only.For any future operand type of AArch64 if not initialised will exit with error "
Unimplemented operand type: MCOI::OperandType:<#Number>
".[Reland Updates]
Updated
tools/llvm-exegesis/AArch64/error-resolution.s
which caused problem.Test case was failing when there is uninitialised operands error coming from secondary/consumer instruction used by exegesis in latency mode required to chain up the assembly to ensure serial execution.
i.e. We get error message like
UMOVvi16_idx0: Not all operands were initialized by the snippet generator for <<<any opcode other than UMOVvi16_idx0>>> opcode.
but test case want to check like# UMOVvi16_idx0_latency: ---
. Thus the testcase fails.[Why it fails (only sometimes)]
Exegesis in latency mode require the generated assembly to be chained to ensure serial execution,
For this exegesis add an additional consumer instruction for some instruction, which is chosen via a random seed.
Thus, it randomly fails whenever there is secondary consumer instruction (which is unsupported/throws error) added in generated assembly.
Please review: @sjoerdmeijer @davemgreen @boomanaiden154 @abhilash1910
Thanks!