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[AMDGPU] Do not use 64-bit literals with VOP3* encodings #156602

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Merged
merged 3 commits into from
Sep 4, 2025
Merged

[AMDGPU] Do not use 64-bit literals with VOP3* encodings #156602

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ed684e8
Tweak test to show one more bogus lit64
jayfoad Sep 3, 2025
dce60d1
[AMDGPU] Do not use 64-bit literals with VOP3* encodings
jayfoad Aug 28, 2025
339afa7
Merge commit 'd29dc18992c8' into vop3-lit64
jayfoad Sep 4, 2025
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22 changes: 13 additions & 9 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -80,8 +80,9 @@ void AMDGPUInstPrinter::printFP64ImmOperand(const MCInst *MI, unsigned OpNo,
const MCSubtargetInfo &STI,
raw_ostream &O) {
// KIMM64
const MCInstrDesc &Desc = MII.get(MI->getOpcode());
uint64_t Imm = MI->getOperand(OpNo).getImm();
printLiteral64(Imm, STI, O, /*IsFP=*/true);
printLiteral64(Desc, Imm, STI, O, /*IsFP=*/true);
}

void AMDGPUInstPrinter::printNamedBit(const MCInst *MI, unsigned OpNo,
Expand Down Expand Up @@ -590,7 +591,7 @@ void AMDGPUInstPrinter::printImmediate32(uint32_t Imm,
O << formatHex(static_cast<uint64_t>(Imm));
}

void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
void AMDGPUInstPrinter::printImmediate64(const MCInstrDesc &Desc, uint64_t Imm,
const MCSubtargetInfo &STI,
raw_ostream &O, bool IsFP) {
int64_t SImm = static_cast<int64_t>(Imm);
Expand Down Expand Up @@ -621,20 +622,23 @@ void AMDGPUInstPrinter::printImmediate64(uint64_t Imm,
STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
O << "0.15915494309189532";
else
printLiteral64(Imm, STI, O, IsFP);
printLiteral64(Desc, Imm, STI, O, IsFP);
}

void AMDGPUInstPrinter::printLiteral64(uint64_t Imm, const MCSubtargetInfo &STI,
void AMDGPUInstPrinter::printLiteral64(const MCInstrDesc &Desc, uint64_t Imm,
const MCSubtargetInfo &STI,
raw_ostream &O, bool IsFP) {
// This part needs to align with AMDGPUOperand::addLiteralImmOperand.
bool CanUse64BitLiterals =
STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
!(Desc.TSFlags & (SIInstrFlags::VOP3 | SIInstrFlags::VOP3P));
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FYI, given the multitude of encodings I was using Desc.getSize() != 4 for that instead. This is the real reason lit64 cannot be used, the instruction itself takes more than a DWORD.

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Nice idea, but in practice that doesn't work for instructions like V_FMAAK_F64. This is VOP2 but Size is set to 12, i.e. the size including the mandatory literal. Changing that feels like a big project...

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Argh, your are right. Maybe I need to check other places.

if (IsFP) {
if (STI.hasFeature(AMDGPU::Feature64BitLiterals) && Lo_32(Imm))
if (CanUse64BitLiterals && Lo_32(Imm))
O << "lit64(" << formatHex(static_cast<uint64_t>(Imm)) << ')';
else
O << formatHex(static_cast<uint64_t>(Hi_32(Imm)));
} else {
if (STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
(!isInt<32>(Imm) || !isUInt<32>(Imm)))
if (CanUse64BitLiterals && (!isInt<32>(Imm) || !isUInt<32>(Imm)))
O << "lit64(" << formatHex(static_cast<uint64_t>(Imm)) << ')';
else
O << formatHex(static_cast<uint64_t>(Imm));
Expand Down Expand Up @@ -749,12 +753,12 @@ void AMDGPUInstPrinter::printRegularOperand(const MCInst *MI, unsigned OpNo,
break;
case AMDGPU::OPERAND_REG_IMM_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
printImmediate64(Op.getImm(), STI, O, false);
printImmediate64(Desc, Op.getImm(), STI, O, false);
break;
case AMDGPU::OPERAND_REG_IMM_FP64:
case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
printImmediate64(Op.getImm(), STI, O, true);
printImmediate64(Desc, Op.getImm(), STI, O, true);
break;
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
case AMDGPU::OPERAND_REG_IMM_INT16:
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h
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Original file line number Diff line number Diff line change
Expand Up @@ -87,10 +87,10 @@ class AMDGPUInstPrinter : public MCInstPrinter {
raw_ostream &O);
void printImmediate32(uint32_t Imm, const MCSubtargetInfo &STI,
raw_ostream &O);
void printImmediate64(uint64_t Imm, const MCSubtargetInfo &STI,
raw_ostream &O, bool IsFP);
void printLiteral64(uint64_t Imm, const MCSubtargetInfo &STI, raw_ostream &O,
bool IsFP);
void printImmediate64(const MCInstrDesc &Desc, uint64_t Imm,
const MCSubtargetInfo &STI, raw_ostream &O, bool IsFP);
void printLiteral64(const MCInstrDesc &Desc, uint64_t Imm,
const MCSubtargetInfo &STI, raw_ostream &O, bool IsFP);
void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
raw_ostream &O);
void printRegularOperand(const MCInst *MI, unsigned OpNo,
Expand Down
34 changes: 17 additions & 17 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -88,7 +88,7 @@ class AMDGPUMCCodeEmitter : public MCCodeEmitter {

/// Encode an fp or int literal.
std::optional<uint64_t>
getLitEncoding(const MCOperand &MO, const MCOperandInfo &OpInfo,
getLitEncoding(const MCInstrDesc &Desc, const MCOperand &MO, unsigned OpNo,
const MCSubtargetInfo &STI,
bool HasMandatoryLiteral = false) const;

Expand Down Expand Up @@ -219,8 +219,8 @@ static uint32_t getLit16IntEncoding(uint32_t Val, const MCSubtargetInfo &STI) {
return getLit32Encoding(Val, STI);
}

static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI,
bool IsFP) {
static uint32_t getLit64Encoding(const MCInstrDesc &Desc, uint64_t Val,
const MCSubtargetInfo &STI, bool IsFP) {
uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
if (IntImm != 0)
return IntImm;
Expand Down Expand Up @@ -255,20 +255,21 @@ static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI,

// The rest part needs to align with AMDGPUInstPrinter::printLiteral64.

bool CanUse64BitLiterals =
STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
!(Desc.TSFlags & (SIInstrFlags::VOP3 | SIInstrFlags::VOP3P));
if (IsFP) {
return STI.hasFeature(AMDGPU::Feature64BitLiterals) && Lo_32(Val) ? 254
: 255;
return CanUse64BitLiterals && Lo_32(Val) ? 254 : 255;
}

return STI.hasFeature(AMDGPU::Feature64BitLiterals) &&
(!isInt<32>(Val) || !isUInt<32>(Val))
? 254
: 255;
return CanUse64BitLiterals && (!isInt<32>(Val) || !isUInt<32>(Val)) ? 254
: 255;
}

std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(
const MCOperand &MO, const MCOperandInfo &OpInfo,
const MCInstrDesc &Desc, const MCOperand &MO, unsigned OpNo,
const MCSubtargetInfo &STI, bool HasMandatoryLiteral) const {
const MCOperandInfo &OpInfo = Desc.operands()[OpNo];
int64_t Imm;
if (MO.isExpr()) {
if (!MO.getExpr()->evaluateAsAbsolute(Imm))
Expand Down Expand Up @@ -296,14 +297,14 @@ std::optional<uint64_t> AMDGPUMCCodeEmitter::getLitEncoding(

case AMDGPU::OPERAND_REG_IMM_INT64:
case AMDGPU::OPERAND_REG_INLINE_C_INT64:
return getLit64Encoding(static_cast<uint64_t>(Imm), STI, false);
return getLit64Encoding(Desc, static_cast<uint64_t>(Imm), STI, false);

case AMDGPU::OPERAND_REG_INLINE_C_FP64:
case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
return getLit64Encoding(static_cast<uint64_t>(Imm), STI, true);
return getLit64Encoding(Desc, static_cast<uint64_t>(Imm), STI, true);

case AMDGPU::OPERAND_REG_IMM_FP64: {
auto Enc = getLit64Encoding(static_cast<uint64_t>(Imm), STI, true);
auto Enc = getLit64Encoding(Desc, static_cast<uint64_t>(Imm), STI, true);
return (HasMandatoryLiteral && Enc == 255) ? 254 : Enc;
}

Expand Down Expand Up @@ -444,7 +445,7 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,

// Is this operand a literal immediate?
const MCOperand &Op = MI.getOperand(i);
auto Enc = getLitEncoding(Op, Desc.operands()[i], STI);
auto Enc = getLitEncoding(Desc, Op, i, STI);
if (!Enc || (*Enc != 255 && *Enc != 254))
continue;

Expand Down Expand Up @@ -518,7 +519,7 @@ void AMDGPUMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
return;
} else {
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI);
auto Enc = getLitEncoding(Desc, MO, OpNo, STI);
if (Enc && *Enc != 255) {
Op = *Enc | SDWA9EncValues::SRC_SGPR_MASK;
return;
Expand Down Expand Up @@ -701,8 +702,7 @@ void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
bool HasMandatoryLiteral =
AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm);
if (auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI,
HasMandatoryLiteral)) {
if (auto Enc = getLitEncoding(Desc, MO, OpNo, STI, HasMandatoryLiteral)) {
Op = *Enc;
return;
}
Expand Down
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