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AMDGPU: Avoid directly using MCOperandInfo RegClass field #156641

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Merged
merged 1 commit into from
Sep 3, 2025
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AMDGPU: Avoid directly using MCOperandInfo RegClass field #156641

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14 changes: 2 additions & 12 deletions llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -193,16 +193,6 @@ MachineOperand *GCNDPPCombine::getOldOpndValue(MachineOperand &OldOpnd) const {
return &OldOpnd;
}

[[maybe_unused]] static unsigned getOperandSize(MachineInstr &MI, unsigned Idx,
MachineRegisterInfo &MRI) {
int16_t RegClass = MI.getDesc().operands()[Idx].RegClass;
if (RegClass == -1)
return 0;

const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
return TRI->getRegSizeInBits(*TRI->getRegClass(RegClass));
}

MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
MachineInstr &MovMI,
RegSubRegPair CombOldVGPR,
Expand Down Expand Up @@ -321,8 +311,8 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI,
// requirements are the same as for src0. We check src0 instead because
// pseudos are shared between subtargets and allow SGPR for src1 on all.
if (!ST->hasDPPSrc1SGPR()) {
assert(getOperandSize(*DPPInst, Src0Idx, *MRI) ==
getOperandSize(*DPPInst, NumOperands, *MRI) &&
assert(TII->getOpSize(*DPPInst, Src0Idx) ==
TII->getOpSize(*DPPInst, NumOperands) &&
"Src0 and Src1 operands should have the same size");
}

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