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[DAG][ARM] canCreateUndefOrPoisonForTargetNode - ARMISD VORRIMM\VBICIMM nodes can't create poison/undef #156831

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Merged
merged 2 commits into from
Sep 5, 2025
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[DAG][ARM] canCreateUndefOrPoisonForTargetNode - ARMISD VORRIMM\VBICIMM nodes can't create poison/undef #156831

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[DAG][ARM] canCreateUndefOrPoisonForTargetNode - ARMISD VORRIMM\VBICI…
woruyu Sep 4, 2025
d10a5f7
fix: review
woruyu Sep 5, 2025
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13 changes: 13 additions & 0 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21363,6 +21363,19 @@ bool ARMTargetLowering::canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
return false;
}

bool ARMTargetLowering::canCreateUndefOrPoisonForTargetNode(
SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const {
unsigned Opcode = Op.getOpcode();
switch (Opcode) {
case ARMISD::VORRIMM:
case ARMISD::VBICIMM:
return false;
}
return TargetLowering::canCreateUndefOrPoisonForTargetNode(
Op, DemandedElts, DAG, PoisonOnly, ConsiderFlags, Depth);
}

bool ARMTargetLowering::isCheapToSpeculateCttz(Type *Ty) const {
return Subtarget->hasV5TOps() && !Subtarget->isThumb1Only();
}
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4 changes: 4 additions & 0 deletions llvm/lib/Target/ARM/ARMISelLowering.h
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Expand Up @@ -707,6 +707,10 @@ class VectorType;
bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
unsigned &Cost) const override;

bool canCreateUndefOrPoisonForTargetNode(
SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG,
bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const override;

bool canMergeStoresTo(unsigned AddressSpace, EVT MemVT,
const MachineFunction &MF) const override {
// Do not merge to larger than i32.
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18 changes: 18 additions & 0 deletions llvm/unittests/Target/ARM/ARMSelectionDAGTest.cpp
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Expand Up @@ -106,6 +106,19 @@ TEST_F(ARMSelectionDAGTest, computeKnownBits_VORRIMM) {
KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
EXPECT_EQ(Known.One, APInt(32, 0xAA));
EXPECT_EQ(Known.Zero, APInt(32, 0x0));

// LHS(per-lane) = 00000000 00000000 00000000 00000000 (0x00000000)
// Encoded(per-lane) = 00000000 00000000 00000000 10101010 (0x000000AA)
// =>
// Known.One = 00000000 00000000 00000000 10101010 (0x000000AA)
// Known.Zero = 11111111 11111111 11111111 01010101 (0x00000000)
SDValue Zero = DAG->getConstant(0, DL, MVT::i32);
SDValue ZeroVec = DAG->getSplatBuildVector(VT, DL, Zero);
Op = DAG->getNode(ARMISD::VORRIMM, DL, VT, ZeroVec, EncSD);
SDValue FrVORRIMM = DAG->getFreeze(Op);
Known = DAG->computeKnownBits(FrVORRIMM);
EXPECT_EQ(Known.One, APInt(32, 0xAA));
EXPECT_EQ(Known.Zero, APInt(32, 0xFFFFFF55));
}

/// VBIC (immediate): x & ~imm with 32-bit elements.
Expand All @@ -129,6 +142,11 @@ TEST_F(ARMSelectionDAGTest, computeKnownBits_VBICIMM) {
KnownBits Known = DAG->computeKnownBits(Op, DemandedElts);
EXPECT_EQ(Known.One, APInt(32, 0xFFFFFF55));
EXPECT_EQ(Known.Zero, APInt(32, 0x000000AA));

SDValue FrVBICIMM = DAG->getFreeze(Op);
Known = DAG->computeKnownBits(FrVBICIMM);
EXPECT_EQ(Known.One, APInt(32, 0xFFFFFF55));
EXPECT_EQ(Known.Zero, APInt(32, 0x000000AA));
}

/// VORR (immediate): per-lane OR with 32-bit elements.
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