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[AVR] Remove some custom decoder functions (NFCI) #156852

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Merged
merged 2 commits into from
Sep 5, 2025
+19 −120
Merged

[AVR] Remove some custom decoder functions (NFCI) #156852

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c14d8fe
[AVR] Remove some custom decoder functions (NFCI)
s-barannikov Sep 4, 2025
55cc4e2
Add comments about valid ranges
s-barannikov Sep 5, 2025
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29 changes: 3 additions & 26 deletions llvm/lib/Target/AVR/AVRInstrFormats.td
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Original file line number Diff line number Diff line change
Expand Up @@ -128,8 +128,6 @@ class FRd<bits<4> opcode, bits<7> f, dag outs, dag ins, string asmstr,
let Inst{11 - 9} = f{6 - 4};
let Inst{8 - 4} = rd;
let Inst{3 - 0} = f{3 - 0};

let DecoderMethod = "decodeFRd";
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -308,8 +306,6 @@ class FIORdA<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10 - 9} = A{5 - 4};
let Inst{8 - 4} = rd;
let Inst{3 - 0} = A{3 - 0};

let DecoderMethod = "decodeFIORdA";
}

//===----------------------------------------------------------------------===//
Expand All @@ -327,8 +323,6 @@ class FIOARr<dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{10 - 9} = A{5 - 4};
let Inst{8 - 4} = rr;
let Inst{3 - 0} = A{3 - 0};

let DecoderMethod = "decodeFIOARr";
}

//===----------------------------------------------------------------------===//
Expand All @@ -343,17 +337,10 @@ class FIOBIT<bits<2> t, dag outs, dag ins, string asmstr, list<dag> pattern>
bits<5> addr;
bits<3> b;

let Inst{15 - 12} = 0b1001;

let Inst{11 - 10} = 0b10;
let Inst{15 - 10} = 0b100110;
let Inst{9 - 8} = t;

let Inst{7 - 4} = addr{4 - 1};

let Inst{3} = addr{0};
let Inst{7 - 3} = addr;
let Inst{2 - 0} = b{2 - 0};

let DecoderMethod = "decodeFIOBIT";
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -412,8 +399,6 @@ class FBRsk<bit f, bits<3> s, dag outs, dag ins, string asmstr,
let Inst{10} = f;
let Inst{9 - 3} = k;
let Inst{2 - 0} = s;

let DecoderMethod = "decodeCondBranch";
}

//===----------------------------------------------------------------------===//
Expand All @@ -437,8 +422,6 @@ class FBRk<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>
let Inst{15 - 13} = 0b110;
let Inst{12} = f;
let Inst{11 - 0} = k;

let DecoderMethod = "decodeFBRk";
}

//===----------------------------------------------------------------------===//
Expand Down Expand Up @@ -532,14 +515,8 @@ class FSK<bit f, dag outs, dag ins, string asmstr, list<dag> pattern>

let Inst{11} = 0;
let Inst{10} = f;
let Inst{9 - 8} = k{6 - 5};

let Inst{7 - 4} = k{4 - 1};

let Inst{3} = k{0};
let Inst{9 - 3} = k;
let Inst{2 - 0} = s;

let DecoderMethod = "decodeCondBranch";
}

class ExtensionPseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AVR/AVRInstrInfo.td
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Expand Up @@ -204,16 +204,19 @@ def memspi : Operand<iPTR> {
def relbrtarget_7 : Operand<OtherVT> {
let PrintMethod = "printPCRelImm";
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_7_pcrel>";
let DecoderMethod = "decodeRelCondBrTarget7";
}

def brtarget_13 : Operand<OtherVT> {
let PrintMethod = "printPCRelImm";
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
let DecoderMethod = "decodeRelCondBrTarget13";
}

def rcalltarget_13 : Operand<i16> {
let PrintMethod = "printPCRelImm";
let EncoderMethod = "encodeRelCondBrTarget<AVR::fixup_13_pcrel>";
let DecoderMethod = "decodeRelCondBrTarget13";
}

// The target of a 22 or 16-bit call/jmp instruction.
Expand Down
107 changes: 13 additions & 94 deletions llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
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Expand Up @@ -97,41 +97,6 @@ static DecodeStatus DecodeZREGRegisterClass(MCInst &Inst,
return MCDisassembler::Success;
}

static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
addr |= fieldFromInstruction(Insn, 0, 4);
addr |= fieldFromInstruction(Insn, 9, 2) << 4;
unsigned reg = fieldFromInstruction(Insn, 4, 5);
Inst.addOperand(MCOperand::createImm(addr));
if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
MCDisassembler::Fail)
return MCDisassembler::Fail;
return MCDisassembler::Success;
}

static DecodeStatus decodeFIORdA(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
addr |= fieldFromInstruction(Insn, 0, 4);
addr |= fieldFromInstruction(Insn, 9, 2) << 4;
unsigned reg = fieldFromInstruction(Insn, 4, 5);
if (DecodeGPR8RegisterClass(Inst, reg, Address, Decoder) ==
MCDisassembler::Fail)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::createImm(addr));
return MCDisassembler::Success;
}

static DecodeStatus decodeFIOBIT(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = fieldFromInstruction(Insn, 3, 5);
unsigned b = fieldFromInstruction(Insn, 0, 3);
Inst.addOperand(MCOperand::createImm(addr));
Inst.addOperand(MCOperand::createImm(b));
return MCDisassembler::Success;
}

static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
uint64_t Address,
const MCDisassembler *Decoder) {
Expand All @@ -141,12 +106,19 @@ static DecodeStatus decodeCallTarget(MCInst &Inst, unsigned Field,
return MCDisassembler::Success;
}

static DecodeStatus decodeFRd(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned d = fieldFromInstruction(Insn, 4, 5);
if (DecodeGPR8RegisterClass(Inst, d, Address, Decoder) ==
MCDisassembler::Fail)
return MCDisassembler::Fail;
static DecodeStatus decodeRelCondBrTarget7(MCInst &Inst, unsigned Field,
uint64_t Address,
const MCDisassembler *Decoder) {
// The legal range is [-128, 126] (in bytes).
Inst.addOperand(MCOperand::createImm(SignExtend32(Field, 7) << 1));
return MCDisassembler::Success;
}

static DecodeStatus decodeRelCondBrTarget13(MCInst &Inst, unsigned Field,
uint64_t Address,
const MCDisassembler *Decoder) {
// The legal range is [-4096, 4094] (in bytes).
Inst.addOperand(MCOperand::createImm(SignExtend32(Field, 12) << 1));
return MCDisassembler::Success;
}

Expand Down Expand Up @@ -225,59 +197,6 @@ static DecodeStatus decodeMemri(MCInst &Inst, unsigned Insn, uint64_t Address,
return MCDisassembler::Success;
}

static DecodeStatus decodeFBRk(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
// Decode the opcode.
switch (Insn & 0xf000) {
case 0xc000:
Inst.setOpcode(AVR::RJMPk);
break;
case 0xd000:
Inst.setOpcode(AVR::RCALLk);
break;
default: // Unknown relative branch instruction.
return MCDisassembler::Fail;
}
// Decode the relative offset.
int16_t Offset = ((int16_t)((Insn & 0xfff) << 4)) >> 3;
Inst.addOperand(MCOperand::createImm(Offset));
return MCDisassembler::Success;
}

static DecodeStatus decodeCondBranch(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
// These 8 instructions are not defined as aliases of BRBS/BRBC.
DenseMap<unsigned, unsigned> brInsts = {
{0x000, AVR::BRLOk}, {0x400, AVR::BRSHk}, {0x001, AVR::BREQk},
{0x401, AVR::BRNEk}, {0x002, AVR::BRMIk}, {0x402, AVR::BRPLk},
{0x004, AVR::BRLTk}, {0x404, AVR::BRGEk}};

// Get the relative offset.
int16_t Offset = ((int16_t)((Insn & 0x3f8) << 6)) >> 8;

// Search the instruction pattern.
auto NotAlias = [&Insn](const std::pair<unsigned, unsigned> &I) {
return (Insn & 0x407) != I.first;
};
llvm::partition(brInsts, NotAlias);
auto It = llvm::partition_point(brInsts, NotAlias);

// Decode the instruction.
if (It != brInsts.end()) {
// This instruction is not an alias of BRBC/BRBS.
Inst.setOpcode(It->second);
Inst.addOperand(MCOperand::createImm(Offset));
} else {
// Fall back to an ordinary BRBS/BRBC.
Inst.setOpcode(Insn & 0x400 ? AVR::BRBCsk : AVR::BRBSsk);
Inst.addOperand(MCOperand::createImm(Insn & 7));
Inst.addOperand(MCOperand::createImm(Offset));
}

return MCDisassembler::Success;
}

static DecodeStatus decodeLoadStore(MCInst &Inst, unsigned Insn,
uint64_t Address,
const MCDisassembler *Decoder) {
Expand Down