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[RISCV] Use arithmetic for select c, 0, simm12 even with zicond #156957

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Merged
merged 3 commits into from
Sep 4, 2025
Merged

[RISCV] Use arithmetic for select c, 0, simm12 even with zicond #156957

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131c831
[RISCV] Use arithmetic for select c, 0, simm12 even with zicond
preames Sep 4, 2025
9f1b090
Merge branch 'main' into pr-riscv-select-of-simm12-and-zero
preames Sep 4, 2025
989d8b1
Address review comment
preames Sep 4, 2025
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18 changes: 18 additions & 0 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9240,6 +9240,10 @@ foldBinOpIntoSelectIfProfitable(SDNode *BO, SelectionDAG &DAG,
return DAG.getSelect(DL, VT, Sel.getOperand(0), NewT, NewF);
}

static bool isSimm12Constant(SDValue V) {
return isa<ConstantSDNode>(V) && V->getAsAPIntVal().isSignedIntN(12);
}

SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
SDValue CondV = Op.getOperand(0);
SDValue TrueV = Op.getOperand(1);
Expand All @@ -9261,6 +9265,20 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
// sequence or RISCVISD::SELECT_CC node (branch-based select).
if ((Subtarget.hasStdExtZicond() || Subtarget.hasVendorXVentanaCondOps()) &&
VT.isScalarInteger()) {

// select c, simm12, 0 -> andi (sub x0, c), simm12
if (isSimm12Constant(TrueV) && isNullConstant(FalseV)) {
SDValue Mask = DAG.getNegative(CondV, DL, VT);
return DAG.getNode(ISD::AND, DL, VT, TrueV, Mask);
}

// select c, 0, simm12 -> andi (addi c, -1), simm12
if (isNullConstant(TrueV) && isSimm12Constant(FalseV)) {
SDValue Mask = DAG.getNode(ISD::ADD, DL, VT, CondV,
DAG.getSignedConstant(-1, DL, XLenVT));
return DAG.getNode(ISD::AND, DL, VT, FalseV, Mask);
}

// (select c, t, 0) -> (czero_eqz t, c)
if (isNullConstant(FalseV))
return DAG.getNode(RISCVISD::CZERO_EQZ, DL, VT, TrueV, CondV);
Expand Down
10 changes: 6 additions & 4 deletions llvm/test/CodeGen/RISCV/cmov-branch-opt.ll
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Expand Up @@ -149,8 +149,9 @@ define signext i32 @test4(i32 signext %x, i32 signext %y, i32 signext %z) {
;
; CMOV-ZICOND-LABEL: test4:
; CMOV-ZICOND: # %bb.0:
; CMOV-ZICOND-NEXT: li a0, 3
; CMOV-ZICOND-NEXT: czero.nez a0, a0, a2
; CMOV-ZICOND-NEXT: snez a0, a2
; CMOV-ZICOND-NEXT: addi a0, a0, -1
; CMOV-ZICOND-NEXT: andi a0, a0, 3
; CMOV-ZICOND-NEXT: ret
;
; SFB-NOZICOND-LABEL: test4:
Expand All @@ -164,8 +165,9 @@ define signext i32 @test4(i32 signext %x, i32 signext %y, i32 signext %z) {
;
; SFB-ZICOND-LABEL: test4:
; SFB-ZICOND: # %bb.0:
; SFB-ZICOND-NEXT: li a0, 3
; SFB-ZICOND-NEXT: czero.nez a0, a0, a2
; SFB-ZICOND-NEXT: snez a0, a2
; SFB-ZICOND-NEXT: addi a0, a0, -1
; SFB-ZICOND-NEXT: andi a0, a0, 3
; SFB-ZICOND-NEXT: ret
%c = icmp eq i32 %z, 0
%a = select i1 %c, i32 3, i32 0
Expand Down
202 changes: 46 additions & 156 deletions llvm/test/CodeGen/RISCV/select-const.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1080,184 +1080,74 @@ define i32 @sext_or_constant2(i32 signext %x) {


define i32 @select_0_6(i32 signext %x) {
; RV32I-LABEL: select_0_6:
; RV32I: # %bb.0:
; RV32I-NEXT: srai a0, a0, 2
; RV32I-NEXT: srli a0, a0, 30
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_0_6:
; RV32IF: # %bb.0:
; RV32IF-NEXT: srai a0, a0, 2
; RV32IF-NEXT: srli a0, a0, 30
; RV32IF-NEXT: slli a0, a0, 1
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: select_0_6:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: li a1, 6
; RV32ZICOND-NEXT: czero.eqz a0, a1, a0
; RV32ZICOND-NEXT: ret
;
; RV64I-LABEL: select_0_6:
; RV64I: # %bb.0:
; RV64I-NEXT: srai a0, a0, 2
; RV64I-NEXT: srli a0, a0, 62
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_0_6:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: srai a0, a0, 2
; RV64IFD-NEXT: srli a0, a0, 62
; RV64IFD-NEXT: slli a0, a0, 1
; RV64IFD-NEXT: ret
; RV32-LABEL: select_0_6:
; RV32: # %bb.0:
; RV32-NEXT: srai a0, a0, 2
; RV32-NEXT: srli a0, a0, 30
; RV32-NEXT: slli a0, a0, 1
; RV32-NEXT: ret
;
; RV64ZICOND-LABEL: select_0_6:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: li a1, 6
; RV64ZICOND-NEXT: czero.eqz a0, a1, a0
; RV64ZICOND-NEXT: ret
; RV64-LABEL: select_0_6:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 2
; RV64-NEXT: srli a0, a0, 62
; RV64-NEXT: slli a0, a0, 1
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 0, i32 6
ret i32 %cond
}

define i32 @select_6_0(i32 signext %x) {
; RV32I-LABEL: select_6_0:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: andi a0, a0, 6
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_6_0:
; RV32IF: # %bb.0:
; RV32IF-NEXT: srli a0, a0, 31
; RV32IF-NEXT: addi a0, a0, -1
; RV32IF-NEXT: andi a0, a0, 6
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: select_6_0:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: li a1, 6
; RV32ZICOND-NEXT: czero.nez a0, a1, a0
; RV32ZICOND-NEXT: ret
;
; RV64I-LABEL: select_6_0:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: andi a0, a0, 6
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_6_0:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: srli a0, a0, 63
; RV64IFD-NEXT: addi a0, a0, -1
; RV64IFD-NEXT: andi a0, a0, 6
; RV64IFD-NEXT: ret
; RV32-LABEL: select_6_0:
; RV32: # %bb.0:
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: andi a0, a0, 6
; RV32-NEXT: ret
;
; RV64ZICOND-LABEL: select_6_0:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: li a1, 6
; RV64ZICOND-NEXT: czero.nez a0, a1, a0
; RV64ZICOND-NEXT: ret
; RV64-LABEL: select_6_0:
; RV64: # %bb.0:
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: andi a0, a0, 6
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 6, i32 0
ret i32 %cond
}

define i32 @select_0_394(i32 signext %x) {
; RV32I-LABEL: select_0_394:
; RV32I: # %bb.0:
; RV32I-NEXT: srai a0, a0, 31
; RV32I-NEXT: andi a0, a0, 394
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_0_394:
; RV32IF: # %bb.0:
; RV32IF-NEXT: srai a0, a0, 31
; RV32IF-NEXT: andi a0, a0, 394
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: select_0_394:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: li a1, 394
; RV32ZICOND-NEXT: czero.eqz a0, a1, a0
; RV32ZICOND-NEXT: ret
;
; RV64I-LABEL: select_0_394:
; RV64I: # %bb.0:
; RV64I-NEXT: srai a0, a0, 63
; RV64I-NEXT: andi a0, a0, 394
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_0_394:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: srai a0, a0, 63
; RV64IFD-NEXT: andi a0, a0, 394
; RV64IFD-NEXT: ret
; RV32-LABEL: select_0_394:
; RV32: # %bb.0:
; RV32-NEXT: srai a0, a0, 31
; RV32-NEXT: andi a0, a0, 394
; RV32-NEXT: ret
;
; RV64ZICOND-LABEL: select_0_394:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: li a1, 394
; RV64ZICOND-NEXT: czero.eqz a0, a1, a0
; RV64ZICOND-NEXT: ret
; RV64-LABEL: select_0_394:
; RV64: # %bb.0:
; RV64-NEXT: srai a0, a0, 63
; RV64-NEXT: andi a0, a0, 394
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 0, i32 394
ret i32 %cond
}

define i32 @select_394_0(i32 signext %x) {
; RV32I-LABEL: select_394_0:
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 31
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: andi a0, a0, 394
; RV32I-NEXT: ret
;
; RV32IF-LABEL: select_394_0:
; RV32IF: # %bb.0:
; RV32IF-NEXT: srli a0, a0, 31
; RV32IF-NEXT: addi a0, a0, -1
; RV32IF-NEXT: andi a0, a0, 394
; RV32IF-NEXT: ret
;
; RV32ZICOND-LABEL: select_394_0:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: srli a0, a0, 31
; RV32ZICOND-NEXT: li a1, 394
; RV32ZICOND-NEXT: czero.nez a0, a1, a0
; RV32ZICOND-NEXT: ret
;
; RV64I-LABEL: select_394_0:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: addi a0, a0, -1
; RV64I-NEXT: andi a0, a0, 394
; RV64I-NEXT: ret
;
; RV64IFD-LABEL: select_394_0:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: srli a0, a0, 63
; RV64IFD-NEXT: addi a0, a0, -1
; RV64IFD-NEXT: andi a0, a0, 394
; RV64IFD-NEXT: ret
; RV32-LABEL: select_394_0:
; RV32: # %bb.0:
; RV32-NEXT: srli a0, a0, 31
; RV32-NEXT: addi a0, a0, -1
; RV32-NEXT: andi a0, a0, 394
; RV32-NEXT: ret
;
; RV64ZICOND-LABEL: select_394_0:
; RV64ZICOND: # %bb.0:
; RV64ZICOND-NEXT: srli a0, a0, 63
; RV64ZICOND-NEXT: li a1, 394
; RV64ZICOND-NEXT: czero.nez a0, a1, a0
; RV64ZICOND-NEXT: ret
; RV64-LABEL: select_394_0:
; RV64: # %bb.0:
; RV64-NEXT: srli a0, a0, 63
; RV64-NEXT: addi a0, a0, -1
; RV64-NEXT: andi a0, a0, 394
; RV64-NEXT: ret
%cmp = icmp sgt i32 %x, -1
%cond = select i1 %cmp, i32 394, i32 0
ret i32 %cond
Expand Down
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