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@arsenm arsenm commented Sep 5, 2025

The management of subtarget dependent assembler errors
is currently ignoring the reported issues from MatchInstructionImpl.
Move code around to try making use of it.

The management of subtarget dependent assembler errors
is currently ignoring the reported issues from MatchInstructionImpl.
Move code around to try making use of it.
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arsenm commented Sep 5, 2025

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llvmbot commented Sep 5, 2025

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

The management of subtarget dependent assembler errors
is currently ignoring the reported issues from MatchInstructionImpl.
Move code around to try making use of it.


Full diff: https://github.com/llvm/llvm-project/pull/157013.diff

1 Files Affected:

  • (modified) llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp (+13-3)
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index fc46f2b6e93dd..522aae08d7353 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1391,6 +1391,7 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
 
 #define GET_ASSEMBLER_HEADER
 #include "AMDGPUGenAsmMatcher.inc"
+#undef GET_ASSEMBLER_HEADER
 
   /// }
 
@@ -2023,6 +2024,12 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
   ParseStatus parseVOPD(OperandVector &Operands);
 };
 
+// TODO: define GET_SUBTARGET_FEATURE_NAME
+#define GET_REGISTER_MATCHER
+#include "AMDGPUGenAsmMatcher.inc"
+#undef GET_REGISTER_MATCHER
+#undef GET_SUBTARGET_FEATURE_NAME
+
 } // end anonymous namespace
 
 // May be called with integer type with equivalent bitwidth.
@@ -5838,10 +5845,14 @@ bool AMDGPUAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   MCInst Inst;
   Inst.setLoc(IDLoc);
   unsigned Result = Match_Success;
+  FeatureBitset MissingFeatures;
+
   for (auto Variant : getMatchedVariants()) {
     uint64_t EI;
-    auto R = MatchInstructionImpl(Operands, Inst, EI, MatchingInlineAsm,
-                                  Variant);
+    auto R = MatchInstructionImpl(Operands, Inst, EI, MissingFeatures,
+                                  MatchingInlineAsm, Variant);
+
+    // TODO: Emit diagnostic from MissingFeatures.
     // We order match statuses from least to most specific. We use most specific
     // status as resulting
     // Match_MnemonicFail < Match_InvalidOperand < Match_MissingFeature
@@ -10497,7 +10508,6 @@ LLVMInitializeAMDGPUAsmParser() {
   RegisterMCAsmParser<AMDGPUAsmParser> B(getTheGCNTarget());
 }
 
-#define GET_REGISTER_MATCHER
 #define GET_MATCHER_IMPLEMENTATION
 #define GET_MNEMONIC_SPELL_CHECKER
 #define GET_MNEMONIC_CHECKER

@arsenm arsenm marked this pull request as ready for review September 5, 2025 05:01
MCInst Inst;
Inst.setLoc(IDLoc);
unsigned Result = Match_Success;
FeatureBitset MissingFeatures;
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Do you need to clear it between loop iterations?

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Kind of yes and kind of no. This loop iteration thing is what prevented me from getting the automatic diagnostics from the predicate. I don't understand why it's here. It fails to match for the right reason on the correct target instruction, but then moves on to the wrong instruction that fails for the wrong reason

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It's not used yet so it doesn't matter

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Well, the whole PR is not used yet, so it does not matter.

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I.e., make a use of it and we will see.

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The point of the PR is so whoever picks this up doesn't have to figure out where in the file to put the .incs

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