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PPC: Move definitions of predicates with features #157058

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Merged
merged 1 commit into from
Sep 16, 2025
Merged

PPC: Move definitions of predicates with features #157058

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37 changes: 37 additions & 0 deletions llvm/lib/Target/PowerPC/PPC.td
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Original file line number Diff line number Diff line change
Expand Up @@ -353,6 +353,43 @@ def FeaturePredictableSelectIsExpensive :
def FeatureFastMFLR : SubtargetFeature<"fast-MFLR", "HasFastMFLR", "true",
"MFLR is a fast instruction">;

//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.
def In32BitMode : Predicate<"!Subtarget->isPPC64()">;
def In64BitMode : Predicate<"Subtarget->isPPC64()">;
def IsBookE : Predicate<"Subtarget->isBookE()">;
def IsNotBookE : Predicate<"!Subtarget->isBookE()">;
def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">;
def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">;
def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">;
def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">;
def IsE500 : Predicate<"Subtarget->isE500()">;
def HasSPE : Predicate<"Subtarget->hasSPE()">;
def HasICBT : Predicate<"Subtarget->hasICBT()">;
def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">;
def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">;
def NoNaNsFPMath
: Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
def NaNsFPMath
: Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
def HasFPU : Predicate<"Subtarget->hasFPU()">;
def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;

// AIX assembler may not be modern enough to support some extended mne.
def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">,
AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>;
def IsAIX : Predicate<"Subtarget->isAIXABI()">;
def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;


// Since new processors generally contain a superset of features of those that
// came before them, the idea is to make implementations of new processors
// less error prone and easier to read.
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36 changes: 0 additions & 36 deletions llvm/lib/Target/PowerPC/PPCInstrInfo.td
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Original file line number Diff line number Diff line change
Expand Up @@ -713,42 +713,6 @@ let WantsParent = true in {
def PDForm : ComplexPattern<iPTR, 2, "SelectPDForm">;
}

//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.
def In32BitMode : Predicate<"!Subtarget->isPPC64()">;
def In64BitMode : Predicate<"Subtarget->isPPC64()">;
def IsBookE : Predicate<"Subtarget->isBookE()">;
def IsNotBookE : Predicate<"!Subtarget->isBookE()">;
def HasOnlyMSYNC : Predicate<"Subtarget->hasOnlyMSYNC()">;
def HasSYNC : Predicate<"!Subtarget->hasOnlyMSYNC()">;
def IsPPC4xx : Predicate<"Subtarget->isPPC4xx()">;
def IsPPC6xx : Predicate<"Subtarget->isPPC6xx()">;
def IsE500 : Predicate<"Subtarget->isE500()">;
def HasSPE : Predicate<"Subtarget->hasSPE()">;
def HasICBT : Predicate<"Subtarget->hasICBT()">;
def HasPartwordAtomics : Predicate<"Subtarget->hasPartwordAtomics()">;
def HasQuadwordAtomics : Predicate<"Subtarget->hasQuadwordAtomics()">;
def NoNaNsFPMath
: Predicate<"Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
def NaNsFPMath
: Predicate<"!Subtarget->getTargetMachine().Options.NoNaNsFPMath">;
def HasBPERMD : Predicate<"Subtarget->hasBPERMD()">;
def HasExtDiv : Predicate<"Subtarget->hasExtDiv()">;
def IsISA2_06 : Predicate<"Subtarget->isISA2_06()">;
def IsISA2_07 : Predicate<"Subtarget->isISA2_07()">;
def IsISA3_0 : Predicate<"Subtarget->isISA3_0()">;
def HasFPU : Predicate<"Subtarget->hasFPU()">;
def PCRelativeMemops : Predicate<"Subtarget->hasPCRelativeMemops()">;
def IsNotISA3_1 : Predicate<"!Subtarget->isISA3_1()">;

// AIX assembler may not be modern enough to support some extended mne.
def ModernAs: Predicate<"!Subtarget->isAIXABI() || Subtarget->HasModernAIXAs">,
AssemblerPredicate<(any_of (not AIXOS), FeatureModernAIXAs)>;
def IsAIX : Predicate<"Subtarget->isAIXABI()">;
def NotAIX : Predicate<"!Subtarget->isAIXABI()">;
def IsISAFuture : Predicate<"Subtarget->isISAFuture()">;
def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;

//===----------------------------------------------------------------------===//
// PowerPC Multiclass Definitions.
multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
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