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[TargetInstrInfo][AArch64] Don't assume register came from operand 0 in canCombine #157210

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Merged
merged 2 commits into from
Sep 6, 2025
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[TargetInstrInfo][AArch64] Don't assume register came from operand 0 in canCombine #157210

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9579c50
[TargetInstrInfo][AArch64] Don't assume register came from operand 0 …
topperc Sep 6, 2025
3461295
fixup! commit test case
topperc Sep 6, 2025
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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/TargetInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -996,7 +996,7 @@ static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO,
(MI->getOpcode() != CombineOpc && CombineOpc != 0))
return false;
// Must only used by the user we combine with.
if (!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
if (!MRI.hasOneNonDBGUse(MO.getReg()))
return false;

return true;
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16 changes: 16 additions & 0 deletions llvm/test/CodeGen/AArch64/pr157118.ll
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@@ -0,0 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=aarch64 < %s | FileCheck %s

define <8 x i8> @test_vaba_u8(<8 x i8> noundef %a, <8 x i8> noundef %b, <8 x i8> noundef %c) {
; CHECK-LABEL: test_vaba_u8:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: //APP
; CHECK-NEXT: //NO_APP
; CHECK-NEXT: uaba v0.8b, v1.8b, v2.8b
; CHECK-NEXT: ret
entry:
%0 = tail call <8 x i8> asm sideeffect "", "=w,0"(<8 x i8> %a)
%vabd.i = tail call <8 x i8> @llvm.aarch64.neon.uabd.v8i8(<8 x i8> %b, <8 x i8> %c)
%add.i = add <8 x i8> %vabd.i, %0
ret <8 x i8> %add.i
}