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[ValueTracking] Don't take sign bit from NaN operands #157250

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Merged
merged 3 commits into from
Sep 16, 2025
Merged

[ValueTracking] Don't take sign bit from NaN operands #157250

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c4fcf16
[ValueTracking] Add pre-commit tests. NFC.
dtcxzyw Sep 6, 2025
6da191e
[ValueTracking] Don't take sign bit from NaN operands
dtcxzyw Sep 6, 2025
e6b8d2a
[ValueTracking] Add commuted tests. NFC.
dtcxzyw Sep 6, 2025
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5 changes: 5 additions & 0 deletions llvm/lib/Analysis/ValueTracking.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5058,6 +5058,11 @@ void computeKnownFPClass(const Value *V, const APInt &DemandedElts,
KnownRHS.isKnownNeverPosZero()) &&
(KnownLHS.isKnownNeverPosZero() ||
KnownRHS.isKnownNeverNegZero()))) {
// Don't take sign bit from NaN operands.
if (!KnownLHS.isKnownNeverNaN())
KnownLHS.SignBit = std::nullopt;
if (!KnownRHS.isKnownNeverNaN())
KnownRHS.SignBit = std::nullopt;
if ((IID == Intrinsic::maximum || IID == Intrinsic::maximumnum ||
IID == Intrinsic::maxnum) &&
(KnownLHS.SignBit == false || KnownRHS.SignBit == false))
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32 changes: 32 additions & 0 deletions llvm/test/Transforms/InstCombine/is_fpclass.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3922,6 +3922,38 @@ define i1 @test_class_is_not_psub_pnorm_pinf__dynamic(float %arg) #3 {
ret i1 %class
}

; Make sure we don't take sign bit from NaN operands.

define i1 @minnum_qnan(i32 %x) {
; CHECK-LABEL: @minnum_qnan(
; CHECK-NEXT: entry:
; CHECK-NEXT: ret i1 true
;
entry:
%qnan_bits = or i32 %x, -5938
%qnan = bitcast i32 %qnan_bits to float
%min = call float @llvm.minnum.f32(float %qnan, float 0.000000e+00)
%test = call i1 @llvm.is.fpclass.f32(float %min, i32 64)
ret i1 %test
}

define i1 @minnum_qnan_commuted(i32 %x, float nofpclass(nnorm nsub nzero ninf nan) %y) {
; CHECK-LABEL: @minnum_qnan_commuted(
; CHECK-NEXT: entry:
; CHECK-NEXT: [[QNAN_BITS:%.*]] = or i32 [[X:%.*]], -5938
; CHECK-NEXT: [[QNAN:%.*]] = bitcast i32 [[QNAN_BITS]] to float
; CHECK-NEXT: [[MIN:%.*]] = call float @llvm.minnum.f32(float [[Y:%.*]], float [[QNAN]])
; CHECK-NEXT: [[TEST:%.*]] = call i1 @llvm.is.fpclass.f32(float [[MIN]], i32 64)
; CHECK-NEXT: ret i1 [[TEST]]
;
entry:
%qnan_bits = or i32 %x, -5938
%qnan = bitcast i32 %qnan_bits to float
%min = call float @llvm.minnum.f32(float %y, float %qnan)
%test = call i1 @llvm.is.fpclass.f32(float %min, i32 64)
ret i1 %test
}

declare i1 @llvm.is.fpclass.f32(float, i32 immarg)
declare i1 @llvm.is.fpclass.f64(double, i32 immarg)
declare <2 x i1> @llvm.is.fpclass.v2f32(<2 x float>, i32 immarg)
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