[RISCV][GISel] Support select vx, vf form rvv intrinsics #157398
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@llvm/pr-subscribers-llvm-globalisel @llvm/pr-subscribers-backend-risc-v Author: Jianjian Guan (jacquesguan) ChangesThis pr is the next step of #156415. For vx form, we legalize it with widen scalar. And for vf form, we select the right register bank. Patch is 114.22 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/157398.diff 7 Files Affected:
diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td
index 878f7b3194830..4d0debd399e5f 100644
--- a/llvm/include/llvm/IR/IntrinsicsRISCV.td
+++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td
@@ -126,6 +126,7 @@ class RISCVVIntrinsic {
Intrinsic IntrinsicID = !cast<Intrinsic>(NAME);
bits<4> ScalarOperand = NoScalarOperand;
bits<5> VLOperand = NoVLOperand;
+ bit IsFPIntrinsic = 0;
}
let TargetPrefix = "riscv" in {
@@ -1442,14 +1443,15 @@ let TargetPrefix = "riscv" in {
defm vwmaccus : RISCVTernaryWide;
defm vwmaccsu : RISCVTernaryWide;
- defm vfadd : RISCVBinaryAAXRoundingMode;
- defm vfsub : RISCVBinaryAAXRoundingMode;
- defm vfrsub : RISCVBinaryAAXRoundingMode;
-
- defm vfwadd : RISCVBinaryABXRoundingMode;
- defm vfwsub : RISCVBinaryABXRoundingMode;
- defm vfwadd_w : RISCVBinaryAAXRoundingMode;
- defm vfwsub_w : RISCVBinaryAAXRoundingMode;
+ let IsFPIntrinsic = 1 in {
+ defm vfadd : RISCVBinaryAAXRoundingMode;
+ defm vfsub : RISCVBinaryAAXRoundingMode;
+ defm vfrsub : RISCVBinaryAAXRoundingMode;
+ defm vfwadd : RISCVBinaryABXRoundingMode;
+ defm vfwsub : RISCVBinaryABXRoundingMode;
+ defm vfwadd_w : RISCVBinaryAAXRoundingMode;
+ defm vfwsub_w : RISCVBinaryAAXRoundingMode;
+ }
defm vsaddu : RISCVSaturatingBinaryAAX;
defm vsadd : RISCVSaturatingBinaryAAX;
@@ -1484,6 +1486,7 @@ let TargetPrefix = "riscv" in {
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
+ let IsFPIntrinsic = 1;
}
def int_riscv_vmv_x_s : DefaultAttrsIntrinsic<[LLVMVectorElementType<0>],
@@ -1506,51 +1509,57 @@ let TargetPrefix = "riscv" in {
llvm_anyint_ty],
[IntrNoMem]>, RISCVVIntrinsic {
let VLOperand = 2;
+ let IsFPIntrinsic = 1;
}
- defm vfmul : RISCVBinaryAAXRoundingMode;
- defm vfdiv : RISCVBinaryAAXRoundingMode;
- defm vfrdiv : RISCVBinaryAAXRoundingMode;
+ let IsFPIntrinsic = 1 in {
+ defm vfmul : RISCVBinaryAAXRoundingMode;
+ defm vfdiv : RISCVBinaryAAXRoundingMode;
+ defm vfrdiv : RISCVBinaryAAXRoundingMode;
- defm vfwmul : RISCVBinaryABXRoundingMode;
+ defm vfwmul : RISCVBinaryABXRoundingMode;
- defm vfmacc : RISCVTernaryAAXARoundingMode;
- defm vfnmacc : RISCVTernaryAAXARoundingMode;
- defm vfmsac : RISCVTernaryAAXARoundingMode;
- defm vfnmsac : RISCVTernaryAAXARoundingMode;
- defm vfmadd : RISCVTernaryAAXARoundingMode;
- defm vfnmadd : RISCVTernaryAAXARoundingMode;
- defm vfmsub : RISCVTernaryAAXARoundingMode;
- defm vfnmsub : RISCVTernaryAAXARoundingMode;
+ defm vfmacc : RISCVTernaryAAXARoundingMode;
+ defm vfnmacc : RISCVTernaryAAXARoundingMode;
+ defm vfmsac : RISCVTernaryAAXARoundingMode;
+ defm vfnmsac : RISCVTernaryAAXARoundingMode;
+ defm vfmadd : RISCVTernaryAAXARoundingMode;
+ defm vfnmadd : RISCVTernaryAAXARoundingMode;
+ defm vfmsub : RISCVTernaryAAXARoundingMode;
+ defm vfnmsub : RISCVTernaryAAXARoundingMode;
- defm vfwmacc : RISCVTernaryWideRoundingMode;
- defm vfwmaccbf16 : RISCVTernaryWideRoundingMode;
- defm vfwnmacc : RISCVTernaryWideRoundingMode;
- defm vfwmsac : RISCVTernaryWideRoundingMode;
- defm vfwnmsac : RISCVTernaryWideRoundingMode;
+ defm vfwmacc : RISCVTernaryWideRoundingMode;
+ defm vfwmaccbf16 : RISCVTernaryWideRoundingMode;
+ defm vfwnmacc : RISCVTernaryWideRoundingMode;
+ defm vfwmsac : RISCVTernaryWideRoundingMode;
+ defm vfwnmsac : RISCVTernaryWideRoundingMode;
- defm vfsqrt : RISCVUnaryAARoundingMode;
- defm vfrsqrt7 : RISCVUnaryAA;
- defm vfrec7 : RISCVUnaryAARoundingMode;
+ defm vfsqrt : RISCVUnaryAARoundingMode;
+ defm vfrsqrt7 : RISCVUnaryAA;
+ defm vfrec7 : RISCVUnaryAARoundingMode;
- defm vfmin : RISCVBinaryAAX;
- defm vfmax : RISCVBinaryAAX;
+ defm vfmin : RISCVBinaryAAX;
+ defm vfmax : RISCVBinaryAAX;
- defm vfsgnj : RISCVBinaryAAX;
- defm vfsgnjn : RISCVBinaryAAX;
- defm vfsgnjx : RISCVBinaryAAX;
+ defm vfsgnj : RISCVBinaryAAX;
+ defm vfsgnjn : RISCVBinaryAAX;
+ defm vfsgnjx : RISCVBinaryAAX;
- defm vfclass : RISCVClassify;
+ defm vfclass : RISCVClassify;
- defm vfmerge : RISCVBinaryWithV0;
+ defm vfmerge : RISCVBinaryWithV0;
+ }
defm vslideup : RVVSlide;
defm vslidedown : RVVSlide;
defm vslide1up : RISCVBinaryAAX;
defm vslide1down : RISCVBinaryAAX;
- defm vfslide1up : RISCVBinaryAAX;
- defm vfslide1down : RISCVBinaryAAX;
+
+ let IsFPIntrinsic = 1 in {
+ defm vfslide1up : RISCVBinaryAAX;
+ defm vfslide1down : RISCVBinaryAAX;
+ }
defm vrgather_vv : RISCVRGatherVV;
defm vrgather_vx : RISCVRGatherVX;
@@ -1571,12 +1580,14 @@ let TargetPrefix = "riscv" in {
defm vnclipu : RISCVSaturatingBinaryABShiftRoundingMode;
defm vnclip : RISCVSaturatingBinaryABShiftRoundingMode;
- defm vmfeq : RISCVCompare;
- defm vmfne : RISCVCompare;
- defm vmflt : RISCVCompare;
- defm vmfle : RISCVCompare;
- defm vmfgt : RISCVCompare;
- defm vmfge : RISCVCompare;
+ let IsFPIntrinsic = 1 in {
+ defm vmfeq : RISCVCompare;
+ defm vmfne : RISCVCompare;
+ defm vmflt : RISCVCompare;
+ defm vmfle : RISCVCompare;
+ defm vmfgt : RISCVCompare;
+ defm vmfge : RISCVCompare;
+ }
defm vredsum : RISCVReduction;
defm vredand : RISCVReduction;
@@ -1590,13 +1601,15 @@ let TargetPrefix = "riscv" in {
defm vwredsumu : RISCVReduction;
defm vwredsum : RISCVReduction;
- defm vfredosum : RISCVReductionRoundingMode;
- defm vfredusum : RISCVReductionRoundingMode;
- defm vfredmin : RISCVReduction;
- defm vfredmax : RISCVReduction;
+ let IsFPIntrinsic = 1 in {
+ defm vfredosum : RISCVReductionRoundingMode;
+ defm vfredusum : RISCVReductionRoundingMode;
+ defm vfredmin : RISCVReduction;
+ defm vfredmax : RISCVReduction;
- defm vfwredusum : RISCVReductionRoundingMode;
- defm vfwredosum : RISCVReductionRoundingMode;
+ defm vfwredusum : RISCVReductionRoundingMode;
+ defm vfwredosum : RISCVReductionRoundingMode;
+ }
def int_riscv_vmand: RISCVBinaryAAAUnMasked;
def int_riscv_vmnand: RISCVBinaryAAAUnMasked;
@@ -1615,31 +1628,33 @@ let TargetPrefix = "riscv" in {
defm vmsof : RISCVMaskedUnaryMOut;
defm vmsif : RISCVMaskedUnaryMOut;
- defm vfcvt_xu_f_v : RISCVConversionRoundingMode;
- defm vfcvt_x_f_v : RISCVConversionRoundingMode;
- defm vfcvt_rtz_xu_f_v : RISCVConversion;
- defm vfcvt_rtz_x_f_v : RISCVConversion;
- defm vfcvt_f_xu_v : RISCVConversionRoundingMode;
- defm vfcvt_f_x_v : RISCVConversionRoundingMode;
-
- defm vfwcvt_f_xu_v : RISCVConversion;
- defm vfwcvt_f_x_v : RISCVConversion;
- defm vfwcvt_xu_f_v : RISCVConversionRoundingMode;
- defm vfwcvt_x_f_v : RISCVConversionRoundingMode;
- defm vfwcvt_rtz_xu_f_v : RISCVConversion;
- defm vfwcvt_rtz_x_f_v : RISCVConversion;
- defm vfwcvt_f_f_v : RISCVConversion;
- defm vfwcvtbf16_f_f_v : RISCVConversion;
-
- defm vfncvt_f_xu_w : RISCVConversionRoundingMode;
- defm vfncvt_f_x_w : RISCVConversionRoundingMode;
- defm vfncvt_xu_f_w : RISCVConversionRoundingMode;
- defm vfncvt_x_f_w : RISCVConversionRoundingMode;
- defm vfncvt_rtz_xu_f_w : RISCVConversion;
- defm vfncvt_rtz_x_f_w : RISCVConversion;
- defm vfncvt_f_f_w : RISCVConversionRoundingMode;
- defm vfncvtbf16_f_f_w : RISCVConversionRoundingMode;
- defm vfncvt_rod_f_f_w : RISCVConversion;
+ let IsFPIntrinsic = 1 in {
+ defm vfcvt_xu_f_v : RISCVConversionRoundingMode;
+ defm vfcvt_x_f_v : RISCVConversionRoundingMode;
+ defm vfcvt_rtz_xu_f_v : RISCVConversion;
+ defm vfcvt_rtz_x_f_v : RISCVConversion;
+ defm vfcvt_f_xu_v : RISCVConversionRoundingMode;
+ defm vfcvt_f_x_v : RISCVConversionRoundingMode;
+
+ defm vfwcvt_f_xu_v : RISCVConversion;
+ defm vfwcvt_f_x_v : RISCVConversion;
+ defm vfwcvt_xu_f_v : RISCVConversionRoundingMode;
+ defm vfwcvt_x_f_v : RISCVConversionRoundingMode;
+ defm vfwcvt_rtz_xu_f_v : RISCVConversion;
+ defm vfwcvt_rtz_x_f_v : RISCVConversion;
+ defm vfwcvt_f_f_v : RISCVConversion;
+ defm vfwcvtbf16_f_f_v : RISCVConversion;
+
+ defm vfncvt_f_xu_w : RISCVConversionRoundingMode;
+ defm vfncvt_f_x_w : RISCVConversionRoundingMode;
+ defm vfncvt_xu_f_w : RISCVConversionRoundingMode;
+ defm vfncvt_x_f_w : RISCVConversionRoundingMode;
+ defm vfncvt_rtz_xu_f_w : RISCVConversion;
+ defm vfncvt_rtz_x_f_w : RISCVConversion;
+ defm vfncvt_f_f_w : RISCVConversionRoundingMode;
+ defm vfncvtbf16_f_f_w : RISCVConversionRoundingMode;
+ defm vfncvt_rod_f_f_w : RISCVConversion;
+ }
// Output: (vector)
// Input: (passthru, mask type input, vl)
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index 16f34a89a52ec..26d47e1ce8d48 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -723,8 +723,27 @@ bool RISCVLegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
- if (RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntrinsicID))
+ if (auto *II = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntrinsicID)) {
+ if (II->hasScalarOperand() && !II->IsFPIntrinsic) {
+ MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
+ MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
+
+ auto OldScalar = MI.getOperand(II->ScalarOperand + 2).getReg();
+ // Legalize integer vx form intrinsic.
+ if (MRI.getType(OldScalar).isScalar()) {
+ if (MRI.getType(OldScalar).getSizeInBits() < sXLen.getSizeInBits()) {
+ Helper.Observer.changingInstr(MI);
+ Helper.widenScalarSrc(MI, sXLen, II->ScalarOperand + 2,
+ TargetOpcode::G_ANYEXT);
+ Helper.Observer.changedInstr(MI);
+ } else if (MRI.getType(OldScalar).getSizeInBits() >
+ sXLen.getSizeInBits()) {
+ // TODO: i64 in riscv32.
+ }
+ }
+ }
return true;
+ }
switch (IntrinsicID) {
default:
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
index a082b18867666..16d6c9a5652d3 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVRegisterBankInfo.cpp
@@ -500,6 +500,34 @@ RISCVRegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
OpdsMapping[1] = GPRValueMapping;
break;
}
+ case TargetOpcode::G_INTRINSIC: {
+ Intrinsic::ID IntrinsicID = cast<GIntrinsic>(MI).getIntrinsicID();
+
+ if (auto *II = RISCVVIntrinsicsTable::getRISCVVIntrinsicInfo(IntrinsicID)) {
+ unsigned ScalarIdx = -1;
+ if (II->hasScalarOperand()) {
+ ScalarIdx = II->ScalarOperand + 2;
+ }
+ for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
+ auto &MO = MI.getOperand(Idx);
+ if (!MO.isReg() || !MO.getReg())
+ continue;
+ LLT Ty = MRI.getType(MO.getReg());
+ if (!Ty.isValid())
+ continue;
+
+ if (Ty.isVector())
+ OpdsMapping[Idx] =
+ getVRBValueMapping(Ty.getSizeInBits().getKnownMinValue());
+ // Chose the right FPR for scalar operand of RVV intrinsics.
+ else if (II->IsFPIntrinsic && ScalarIdx == Idx)
+ OpdsMapping[Idx] = getFPValueMapping(Ty.getSizeInBits());
+ else
+ OpdsMapping[Idx] = GPRValueMapping;
+ }
+ }
+ break;
+ }
default:
// By default map all scalars to GPR.
for (unsigned Idx = 0; Idx < NumOperands; ++Idx) {
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 4581c11356aff..3f81ed74c12ed 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -642,6 +642,7 @@ struct RISCVVIntrinsicInfo {
unsigned IntrinsicID;
uint8_t ScalarOperand;
uint8_t VLOperand;
+ bool IsFPIntrinsic;
bool hasScalarOperand() const {
// 0xF is not valid. See NoScalarOperand in IntrinsicsRISCV.td.
return ScalarOperand != 0xF;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index 03e6f43a38945..ecde628fc7e21 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -575,7 +575,7 @@ def RISCVVInversePseudosTable : GenericTable {
def RISCVVIntrinsicsTable : GenericTable {
let FilterClass = "RISCVVIntrinsic";
let CppTypeName = "RISCVVIntrinsicInfo";
- let Fields = ["IntrinsicID", "ScalarOperand", "VLOperand"];
+ let Fields = ["IntrinsicID", "ScalarOperand", "VLOperand", "IsFPIntrinsic"];
let PrimaryKey = ["IntrinsicID"];
let PrimaryKeyName = "getRISCVVIntrinsicInfo";
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
new file mode 100644
index 0000000000000..56616c286b6d8
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/rvv/vadd.ll
@@ -0,0 +1,2443 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v -global-isel \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v -global-isel \
+; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK
+
+declare <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
+ <vscale x 1 x i8>,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i8>,
+ iXLen);
+
+define <vscale x 1 x i8> @intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv1i8_nxv1i8_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i8> @llvm.riscv.vadd.nxv1i8.nxv1i8(
+ <vscale x 1 x i8> undef,
+ <vscale x 1 x i8> %0,
+ <vscale x 1 x i8> %1,
+ iXLen %2)
+
+ ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
+ <vscale x 1 x i8>,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i8>,
+ <vscale x 1 x i1>,
+ iXLen, iXLen);
+
+define <vscale x 1 x i8> @intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i8> %1, <vscale x 1 x i8> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv1i8_nxv1i8_nxv1i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 1 x i8> @llvm.riscv.vadd.mask.nxv1i8.nxv1i8(
+ <vscale x 1 x i8> %0,
+ <vscale x 1 x i8> %1,
+ <vscale x 1 x i8> %2,
+ <vscale x 1 x i1> %3,
+ iXLen %4, iXLen 1)
+
+ ret <vscale x 1 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
+ <vscale x 2 x i8>,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i8>,
+ iXLen);
+
+define <vscale x 2 x i8> @intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv2i8_nxv2i8_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i8> @llvm.riscv.vadd.nxv2i8.nxv2i8(
+ <vscale x 2 x i8> undef,
+ <vscale x 2 x i8> %0,
+ <vscale x 2 x i8> %1,
+ iXLen %2)
+
+ ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
+ <vscale x 2 x i8>,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i8>,
+ <vscale x 2 x i1>,
+ iXLen, iXLen);
+
+define <vscale x 2 x i8> @intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i8> %1, <vscale x 2 x i8> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv2i8_nxv2i8_nxv2i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 2 x i8> @llvm.riscv.vadd.mask.nxv2i8.nxv2i8(
+ <vscale x 2 x i8> %0,
+ <vscale x 2 x i8> %1,
+ <vscale x 2 x i8> %2,
+ <vscale x 2 x i1> %3,
+ iXLen %4, iXLen 1)
+
+ ret <vscale x 2 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
+ <vscale x 4 x i8>,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i8>,
+ iXLen);
+
+define <vscale x 4 x i8> @intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv4i8_nxv4i8_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x i8> @llvm.riscv.vadd.nxv4i8.nxv4i8(
+ <vscale x 4 x i8> undef,
+ <vscale x 4 x i8> %0,
+ <vscale x 4 x i8> %1,
+ iXLen %2)
+
+ ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
+ <vscale x 4 x i8>,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i8>,
+ <vscale x 4 x i1>,
+ iXLen, iXLen);
+
+define <vscale x 4 x i8> @intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i8> %1, <vscale x 4 x i8> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv4i8_nxv4i8_nxv4i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 4 x i8> @llvm.riscv.vadd.mask.nxv4i8.nxv4i8(
+ <vscale x 4 x i8> %0,
+ <vscale x 4 x i8> %1,
+ <vscale x 4 x i8> %2,
+ <vscale x 4 x i1> %3,
+ iXLen %4, iXLen 1)
+
+ ret <vscale x 4 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
+ <vscale x 8 x i8>,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i8>,
+ iXLen);
+
+define <vscale x 8 x i8> @intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v9
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x i8> @llvm.riscv.vadd.nxv8i8.nxv8i8(
+ <vscale x 8 x i8> undef,
+ <vscale x 8 x i8> %0,
+ <vscale x 8 x i8> %1,
+ iXLen %2)
+
+ ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ <vscale x 8 x i8>,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i8>,
+ <vscale x 8 x i1>,
+ iXLen, iXLen);
+
+define <vscale x 8 x i8> @intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i8> %1, <vscale x 8 x i8> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
+; CHECK-LABEL: intrinsic_vadd_mask_vv_nxv8i8_nxv8i8_nxv8i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 8 x i8> @llvm.riscv.vadd.mask.nxv8i8.nxv8i8(
+ <vscale x 8 x i8> %0,
+ <vscale x 8 x i8> %1,
+ <vscale x 8 x i8> %2,
+ <vscale x 8 x i1> %3,
+ iXLen %4, iXLen 1)
+
+ ret <vscale x 8 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
+ <vscale x 16 x i8>,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i8>,
+ iXLen);
+
+define <vscale x 16 x i8> @intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i8> %1, iXLen %2) nounwind {
+; CHECK-LABEL: intrinsic_vadd_vv_nxv16i8_nxv16i8_nxv16i8:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
+; CHECK-NEXT: vadd.vv v8, v8, v10
+; CHECK-NEXT: ret
+entry:
+ %a = call <vscale x 16 x i8> @llvm.riscv.vadd.nxv16i8.nxv16i8(
+ <vscale x 16 x i8> undef,
+ <vscale x 16 x i8> %0,
+ <vscale x 16 x i8> %1,
+ iXLen %2)
+
+ ret <vscale x 16 x i8> %a
+}
+
+declare <vscale x 16 x i8> @llvm.riscv.vadd.mask.nxv16i8.nxv16i8(
+ <vscale x 16 x i8>,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i8>,
+ <vscale x 16 x i1>,
+ iXLen, iXLen);
+
+define <vscale ...
[truncated]
|
arsenm
reviewed
Sep 12, 2025
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These also probably should not be possible
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The intrinsic ID is not a reg.
For vx form, we legalize it with widen scalar. And for vf form, we select the right register bank.
jacquesguan
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topperc
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Sep 17, 2025
| Helper.Observer.changedInstr(MI); | ||
| } else if (MRI.getType(OldScalar).getSizeInBits() > | ||
| sXLen.getSizeInBits()) { | ||
| // TODO: i64 in riscv32. |
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Should we return false here so it fails?
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Addressed, added a return.
YixingZhang007
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to YixingZhang007/llvm-project
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Sep 27, 2025
For vx form, we legalize it with widen scalar. And for vf form, we select the right register bank.
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This pr is the next step of #156415. For vx form, we legalize it with widen scalar. And for vf form, we select the right register bank.