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X86: Avoid using isArch64Bit for 64-bit checks #157412

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Merged
merged 2 commits into from
Sep 19, 2025
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X86: Avoid using isArch64Bit for 64-bit checks #157412

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6cecbb8
X86: Avoid using isArch64Bit for 64-bit checks
arsenm Sep 8, 2025
8bf1253
new triple checks
arsenm Sep 11, 2025
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6 changes: 6 additions & 0 deletions llvm/include/llvm/TargetParser/Triple.h
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Expand Up @@ -1103,6 +1103,12 @@ class Triple {
return getArch() == Triple::x86 || getArch() == Triple::x86_64;
}

/// Tests whether the target is x86 (32-bit).
bool isX86_32() const { return getArch() == Triple::x86; }

/// Tests whether the target is x86 (64-bit).
bool isX86_64() const { return getArch() == Triple::x86_64; }
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@phoebewang can your downstream targets modify and use this OK?

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Yeah, I think it's OK. Thanks!


/// Tests whether the target is VE
bool isVE() const {
return getArch() == Triple::ve;
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4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp
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Expand Up @@ -559,7 +559,7 @@ void X86AsmBackend::emitInstructionEnd(MCObjectStreamer &OS,
std::optional<MCFixupKind> X86AsmBackend::getFixupKind(StringRef Name) const {
if (STI.getTargetTriple().isOSBinFormatELF()) {
unsigned Type;
if (STI.getTargetTriple().getArch() == Triple::x86_64) {
if (STI.getTargetTriple().isX86_64()) {
Type = llvm::StringSwitch<unsigned>(Name)
#define ELF_RELOC(X, Y) .Case(#X, Y)
#include "llvm/BinaryFormat/ELFRelocs/x86_64.def"
Expand Down Expand Up @@ -1286,7 +1286,7 @@ class DarwinX86AsmBackend : public X86AsmBackend {
DarwinX86AsmBackend(const Target &T, const MCRegisterInfo &MRI,
const MCSubtargetInfo &STI)
: X86AsmBackend(T, STI), MRI(MRI), TT(STI.getTargetTriple()),
Is64Bit(TT.isArch64Bit()) {
Is64Bit(TT.isX86_64()) {
memset(SavedRegs, 0, sizeof(SavedRegs));
OffsetSize = Is64Bit ? 8 : 4;
MoveInstrSize = Is64Bit ? 3 : 2;
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8 changes: 4 additions & 4 deletions llvm/lib/Target/X86/MCTargetDesc/X86MCAsmInfo.cpp
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Expand Up @@ -68,7 +68,7 @@ const MCAsmInfo::AtSpecifier atSpecifiers[] = {
void X86MCAsmInfoDarwin::anchor() { }

X86MCAsmInfoDarwin::X86MCAsmInfoDarwin(const Triple &T) {
bool is64Bit = T.getArch() == Triple::x86_64;
bool is64Bit = T.isX86_64();
if (is64Bit)
CodePointerSize = CalleeSaveStackSlotSize = 8;

Expand Down Expand Up @@ -113,7 +113,7 @@ X86_64MCAsmInfoDarwin::X86_64MCAsmInfoDarwin(const Triple &Triple)
void X86ELFMCAsmInfo::anchor() { }

X86ELFMCAsmInfo::X86ELFMCAsmInfo(const Triple &T) {
bool is64Bit = T.getArch() == Triple::x86_64;
bool is64Bit = T.isX86_64();
bool isX32 = T.isX32();

// For ELF, x86-64 pointer size depends on the ABI.
Expand Down Expand Up @@ -149,7 +149,7 @@ X86_64MCAsmInfoDarwin::getExprForPersonalitySymbol(const MCSymbol *Sym,
void X86MCAsmInfoMicrosoft::anchor() { }

X86MCAsmInfoMicrosoft::X86MCAsmInfoMicrosoft(const Triple &Triple) {
if (Triple.getArch() == Triple::x86_64) {
if (Triple.isX86_64()) {
PrivateGlobalPrefix = ".L";
PrivateLabelPrefix = ".L";
CodePointerSize = 8;
Expand Down Expand Up @@ -189,7 +189,7 @@ void X86MCAsmInfoGNUCOFF::anchor() { }
X86MCAsmInfoGNUCOFF::X86MCAsmInfoGNUCOFF(const Triple &Triple) {
assert((Triple.isOSWindows() || Triple.isUEFI()) &&
"Windows and UEFI are the only supported COFF targets");
if (Triple.getArch() == Triple::x86_64) {
if (Triple.isX86_64()) {
PrivateGlobalPrefix = ".L";
PrivateLabelPrefix = ".L";
CodePointerSize = 8;
Expand Down
11 changes: 5 additions & 6 deletions llvm/lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp
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Expand Up @@ -48,7 +48,7 @@ std::string X86_MC::ParseX86Triple(const Triple &TT) {
std::string FS;
// SSE2 should default to enabled in 64-bit mode, but can be turned off
// explicitly.
if (TT.isArch64Bit())
if (TT.isX86_64())
FS = "+64bit-mode,-32bit-mode,-16bit-mode,+sse2";
else if (TT.getEnvironment() != Triple::CODE16)
FS = "-64bit-mode,+32bit-mode,-16bit-mode";
Expand All @@ -59,7 +59,7 @@ std::string X86_MC::ParseX86Triple(const Triple &TT) {
}

unsigned X86_MC::getDwarfRegFlavour(const Triple &TT, bool isEH) {
if (TT.getArch() == Triple::x86_64)
if (TT.isX86_64())
return DWARFFlavour::X86_64;

if (TT.isOSDarwin())
Expand Down Expand Up @@ -407,9 +407,8 @@ static MCInstrInfo *createX86MCInstrInfo() {
}

static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
unsigned RA = (TT.getArch() == Triple::x86_64)
? X86::RIP // Should have dwarf #16.
: X86::EIP; // Should have dwarf #8.
unsigned RA = TT.isX86_64() ? X86::RIP // Should have dwarf #16.
: X86::EIP; // Should have dwarf #8.

MCRegisterInfo *X = new MCRegisterInfo();
InitX86MCRegisterInfo(X, RA, X86_MC::getDwarfRegFlavour(TT, false),
Expand All @@ -421,7 +420,7 @@ static MCRegisterInfo *createX86MCRegisterInfo(const Triple &TT) {
static MCAsmInfo *createX86MCAsmInfo(const MCRegisterInfo &MRI,
const Triple &TheTriple,
const MCTargetOptions &Options) {
bool is64Bit = TheTriple.getArch() == Triple::x86_64;
bool is64Bit = TheTriple.isX86_64();

MCAsmInfo *MAI;
if (TheTriple.isOSBinFormatMachO()) {
Expand Down
8 changes: 4 additions & 4 deletions llvm/lib/Target/X86/X86AsmPrinter.cpp
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Expand Up @@ -194,7 +194,7 @@ void X86AsmPrinter::emitKCFITypeId(const MachineFunction &MF) {
if (F.getParent()->getModuleFlag("kcfi-arity")) {
// The ArityToRegMap assumes the 64-bit SysV ABI.
[[maybe_unused]] const auto &Triple = MF.getTarget().getTargetTriple();
assert(Triple.isArch64Bit() && !Triple.isOSWindows());
assert(Triple.isX86_64() && !Triple.isOSWindows());

// Determine the function's arity (i.e., the number of arguments) at the ABI
// level by counting the number of parameters that are passed
Expand Down Expand Up @@ -897,15 +897,15 @@ void X86AsmPrinter::emitStartOfAsmFile(Module &M) {

if (FeatureFlagsAnd) {
// Emit a .note.gnu.property section with the flags.
assert((TT.isArch32Bit() || TT.isArch64Bit()) &&
assert((TT.isX86_32() || TT.isX86_64()) &&
"CFProtection used on invalid architecture!");
MCSection *Cur = OutStreamer->getCurrentSectionOnly();
MCSection *Nt = MMI->getContext().getELFSection(
".note.gnu.property", ELF::SHT_NOTE, ELF::SHF_ALLOC);
OutStreamer->switchSection(Nt);

// Emitting note header.
const int WordSize = TT.isArch64Bit() && !TT.isX32() ? 8 : 4;
const int WordSize = TT.isX86_64() && !TT.isX32() ? 8 : 4;
emitAlignment(WordSize == 4 ? Align(4) : Align(8));
OutStreamer->emitIntValue(4, 4 /*size*/); // data size for "GNU\0"
OutStreamer->emitIntValue(8 + WordSize, 4 /*size*/); // Elf_Prop size
Expand Down Expand Up @@ -1089,7 +1089,7 @@ void X86AsmPrinter::emitEndOfAsmFile(Module &M) {
}

// Emit __morestack address if needed for indirect calls.
if (TT.getArch() == Triple::x86_64 && TM.getCodeModel() == CodeModel::Large) {
if (TT.isX86_64() && TM.getCodeModel() == CodeModel::Large) {
if (MCSymbol *AddrSymbol = OutContext.lookupSymbol("__morestack_addr")) {
Align Alignment(1);
MCSection *ReadOnlySection = getObjFileLowering().getSectionForConstant(
Expand Down
4 changes: 2 additions & 2 deletions llvm/lib/Target/X86/X86IndirectThunks.cpp
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Expand Up @@ -115,7 +115,7 @@ bool RetpolineThunkInserter::insertThunks(MachineModuleInfo &MMI,
bool ExistingThunks) {
if (ExistingThunks)
return false;
if (MMI.getTarget().getTargetTriple().getArch() == Triple::x86_64)
if (MMI.getTarget().getTargetTriple().isX86_64())
createThunkFunction(MMI, R11RetpolineName);
else
for (StringRef Name : {EAXRetpolineName, ECXRetpolineName, EDXRetpolineName,
Expand All @@ -125,7 +125,7 @@ bool RetpolineThunkInserter::insertThunks(MachineModuleInfo &MMI,
}

void RetpolineThunkInserter::populateThunk(MachineFunction &MF) {
bool Is64Bit = MF.getTarget().getTargetTriple().getArch() == Triple::x86_64;
bool Is64Bit = MF.getTarget().getTargetTriple().isX86_64();
Register ThunkReg;
if (Is64Bit) {
assert(MF.getName() == "__llvm_retpoline_r11" &&
Expand Down
6 changes: 3 additions & 3 deletions llvm/lib/Target/X86/X86RegisterInfo.cpp
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Expand Up @@ -53,14 +53,14 @@ static cl::opt<bool>
extern cl::opt<bool> X86EnableAPXForRelocation;

X86RegisterInfo::X86RegisterInfo(const Triple &TT)
: X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
: X86GenRegisterInfo((TT.isX86_64() ? X86::RIP : X86::EIP),
X86_MC::getDwarfRegFlavour(TT, false),
X86_MC::getDwarfRegFlavour(TT, true),
(TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
(TT.isX86_64() ? X86::RIP : X86::EIP)) {
X86_MC::initLLVMToSEHAndCVRegMapping(this);

// Cache some information.
Is64Bit = TT.isArch64Bit();
Is64Bit = TT.isX86_64();
IsTarget64BitLP64 = Is64Bit && !TT.isX32();
IsWin64 = Is64Bit && TT.isOSWindows();
IsUEFI64 = Is64Bit && TT.isUEFI();
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/X86/X86ReturnThunks.cpp
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Expand Up @@ -68,7 +68,7 @@ bool X86ReturnThunks::runOnMachineFunction(MachineFunction &MF) {
return Modified;

const auto &ST = MF.getSubtarget<X86Subtarget>();
const bool Is64Bit = ST.getTargetTriple().getArch() == Triple::x86_64;
const bool Is64Bit = ST.getTargetTriple().isX86_64();
const unsigned RetOpc = Is64Bit ? X86::RET64 : X86::RET32;
SmallVector<MachineInstr *, 16> Rets;

Expand Down
16 changes: 8 additions & 8 deletions llvm/lib/Target/X86/X86TargetMachine.cpp
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Expand Up @@ -112,22 +112,22 @@ extern "C" LLVM_C_ABI void LLVMInitializeX86Target() {

static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
if (TT.isOSBinFormatMachO()) {
if (TT.getArch() == Triple::x86_64)
if (TT.isX86_64())
return std::make_unique<X86_64MachoTargetObjectFile>();
return std::make_unique<TargetLoweringObjectFileMachO>();
}

if (TT.isOSBinFormatCOFF())
return std::make_unique<TargetLoweringObjectFileCOFF>();

if (TT.getArch() == Triple::x86_64)
if (TT.isX86_64())
return std::make_unique<X86_64ELFTargetObjectFile>();
return std::make_unique<X86ELFTargetObjectFile>();
}

static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
std::optional<Reloc::Model> RM) {
bool is64Bit = TT.getArch() == Triple::x86_64;
bool is64Bit = TT.isX86_64();
if (!RM) {
// JIT codegen should use static relocations by default, since it's
// typically executed in process and not relocatable.
Expand Down Expand Up @@ -169,7 +169,7 @@ static Reloc::Model getEffectiveRelocModel(const Triple &TT, bool JIT,
static CodeModel::Model
getEffectiveX86CodeModel(const Triple &TT, std::optional<CodeModel::Model> CM,
bool JIT) {
bool Is64Bit = TT.getArch() == Triple::x86_64;
bool Is64Bit = TT.isX86_64();
if (CM) {
if (*CM == CodeModel::Tiny)
reportFatalUsageError("target does not support the tiny CodeModel");
Expand Down Expand Up @@ -440,7 +440,7 @@ void X86PassConfig::addIRPasses() {
// Add Control Flow Guard checks.
const Triple &TT = TM->getTargetTriple();
if (TT.isOSWindows()) {
if (TT.getArch() == Triple::x86_64) {
if (TT.isX86_64()) {
addPass(createCFGuardDispatchPass());
} else {
addPass(createCFGuardCheckPass());
Expand Down Expand Up @@ -499,7 +499,7 @@ bool X86PassConfig::addILPOpts() {
bool X86PassConfig::addPreISel() {
// Only add this pass for 32-bit x86 Windows.
const Triple &TT = TM->getTargetTriple();
if (TT.isOSWindows() && TT.getArch() == Triple::x86)
if (TT.isOSWindows() && TT.isX86_32())
addPass(createX86WinEHStatePass());
return true;
}
Expand Down Expand Up @@ -588,7 +588,7 @@ void X86PassConfig::addPreEmitPass2() {

// Insert extra int3 instructions after trailing call instructions to avoid
// issues in the unwinder.
if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
if (TT.isOSWindows() && TT.isX86_64())
addPass(createX86AvoidTrailingCallPass());

// Verify basic block incoming and outgoing cfa offset and register values and
Expand Down Expand Up @@ -625,7 +625,7 @@ void X86PassConfig::addPreEmitPass2() {

// Analyzes and emits pseudos to support Win x64 Unwind V2. This pass must run
// after all real instructions have been added to the epilog.
if (TT.isOSWindows() && (TT.getArch() == Triple::x86_64))
if (TT.isOSWindows() && TT.isX86_64())
addPass(createX86WinEHUnwindV2Pass());
}

Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/TargetParser/TargetDataLayout.cpp
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Expand Up @@ -379,7 +379,7 @@ static std::string computeSystemZDataLayout(const Triple &TT) {
}

static std::string computeX86DataLayout(const Triple &TT) {
bool Is64Bit = TT.getArch() == Triple::x86_64;
bool Is64Bit = TT.isX86_64();

// X86 is little endian
std::string Ret = "e";
Expand Down