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Sparc: Add 64-bit feature #157445

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Merged
merged 1 commit into from
Sep 8, 2025
Merged

Sparc: Add 64-bit feature #157445

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12 changes: 10 additions & 2 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -81,8 +81,16 @@ static MCRegisterInfo *createSparcMCRegisterInfo(const Triple &TT) {
static MCSubtargetInfo *
createSparcMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
if (CPU.empty())
CPU = (TT.getArch() == Triple::sparcv9) ? "v9" : "v8";
return createSparcMCSubtargetInfoImpl(TT, CPU, /*TuneCPU*/ CPU, FS);
CPU = TT.getArch() == Triple::sparcv9 ? "v9" : "v8";

MCSubtargetInfo *STI =
createSparcMCSubtargetInfoImpl(TT, CPU, /*TuneCPU=*/CPU, FS);
if (TT.isSPARC64() && !STI->hasFeature(Sparc::Feature64Bit)) {
FeatureBitset Features = STI->getFeatureBits();
STI->setFeatureBits(Features.set(Sparc::Feature64Bit));
}

return STI;
}

static MCTargetStreamer *
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1 change: 1 addition & 0 deletions llvm/lib/Target/Sparc/MCTargetDesc/SparcMCTargetDesc.h
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Expand Up @@ -28,6 +28,7 @@ class MCRegisterInfo;
class MCSubtargetInfo;
class MCTargetOptions;
class Target;
class Triple;

MCCodeEmitter *createSparcMCCodeEmitter(const MCInstrInfo &MCII,
MCContext &Ctx);
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3 changes: 3 additions & 0 deletions llvm/lib/Target/Sparc/Sparc.td
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Expand Up @@ -34,6 +34,9 @@ def FeatureNoFMULS
def FeatureV9
: SubtargetFeature<"v9", "IsV9", "true",
"Enable SPARC-V9 instructions">;
def Feature64Bit : SubtargetFeature<"64bit", "Is64Bit", "true",
"Enable 64-bit mode", [FeatureV9]>;

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Is64Bit predicate in SparcInstrInfo.td should be changed to use this feature.

def FeatureV8Plus
: SubtargetFeature<"v8plus", "IsV8Plus", "true",
"Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit code">;
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10 changes: 8 additions & 2 deletions llvm/lib/Target/Sparc/SparcSubtarget.cpp
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Expand Up @@ -28,17 +28,24 @@ void SparcSubtarget::anchor() { }

SparcSubtarget &SparcSubtarget::initializeSubtargetDependencies(
StringRef CPU, StringRef TuneCPU, StringRef FS) {
const Triple &TT = getTargetTriple();
// Determine default and user specified characteristics
std::string CPUName = std::string(CPU);
if (CPUName.empty())
CPUName = getTargetTriple().isSPARC64() ? "v9" : "v8";
CPUName = TT.isSPARC64() ? "v9" : "v8";

if (TuneCPU.empty())
TuneCPU = CPUName;

// Parse features string.
ParseSubtargetFeatures(CPUName, TuneCPU, FS);

if (!Is64Bit && TT.isSPARC64()) {
FeatureBitset Features = getFeatureBits();
setFeatureBits(Features.set(Sparc::Feature64Bit));
Is64Bit = true;
}

// Popc is a v9-only instruction.
if (!IsV9)
UsePopc = false;
Expand All @@ -50,7 +57,6 @@ SparcSubtarget::SparcSubtarget(const StringRef &CPU, const StringRef &TuneCPU,
const StringRef &FS, const TargetMachine &TM)
: SparcGenSubtargetInfo(TM.getTargetTriple(), CPU, TuneCPU, FS),
ReserveRegister(TM.getMCRegisterInfo()->getNumRegs()),
Is64Bit(TM.getTargetTriple().isSPARC64()),
InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
TLInfo(TM, *this), FrameLowering(*this) {
TSInfo = std::make_unique<SparcSelectionDAGInfo>();
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4 changes: 0 additions & 4 deletions llvm/lib/Target/Sparc/SparcSubtarget.h
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Expand Up @@ -36,8 +36,6 @@ class SparcSubtarget : public SparcGenSubtargetInfo {

virtual void anchor();

const bool Is64Bit;

#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
bool ATTRIBUTE = DEFAULT;
#include "SparcGenSubtargetInfo.inc"
Expand Down Expand Up @@ -79,8 +77,6 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
StringRef TuneCPU,
StringRef FS);

bool is64Bit() const { return Is64Bit; }

/// The 64-bit ABI uses biased stack and frame pointers, so the stack frame
/// of the current function is the area from [%sp+BIAS] to [%fp+BIAS].
int64_t getStackPointerBias() const {
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