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POC decoder namespace coalescing #157753

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11 changes: 11 additions & 0 deletions llvm/include/llvm/Target/Target.td
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Expand Up @@ -1154,6 +1154,17 @@ class InstrInfo {
//
// This option is a temporary migration help. It will go away.
bit guessInstructionProperties = true;

// Lists of decoder namespaces to coalesce. Each list should consist of one
// or more names, and the meaning is that each namespace is coalesced with
// the first namespace in the list. And the order of the namespaces in the
// list is the attempt order. As an example, if we have
// [ "", "X", "Y" ]
// Then namespaces X and Y are coalesced with "", and the decoding is
// attempted in the order "", then X and then Y.
// FIXME: Does this need to be done per HWmode, since the decoder tables
// are generated per HW mode.
list<list<string>> CoalesceDecoderNamespaces = [[]];
}

// Standard Pseudo Instructions.
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3 changes: 0 additions & 3 deletions llvm/lib/Bitcode/Reader/MetadataLoader.cpp
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Expand Up @@ -58,9 +58,6 @@
#include <tuple>
#include <utility>
#include <vector>
namespace llvm {
class Argument;
}

using namespace llvm;

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5 changes: 4 additions & 1 deletion llvm/lib/Target/AArch64/AArch64.td
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Expand Up @@ -40,7 +40,10 @@ include "AArch64SchedPredExynos.td"
include "AArch64SchedPredNeoverse.td"
include "AArch64Combine.td"

def AArch64InstrInfo : InstrInfo;
def AArch64InstrInfo : InstrInfo {
// Coalesce "Fallback" and default "" namespaces.
let CoalesceDecoderNamespaces = [["", "Fallback" ]];
}

//===----------------------------------------------------------------------===//
// Named operands for MRS/MSR/TLBI/...
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
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Expand Up @@ -1608,7 +1608,7 @@ DecodeStatus AArch64Disassembler::getInstruction(MCInst &MI, uint64_t &Size,
uint32_t Insn =
(Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0);

const uint8_t *Tables[] = {DecoderTable32, DecoderTableFallback32};
const uint8_t *Tables[] = {DecoderTable32};

for (const auto *Table : Tables) {
DecodeStatus Result =
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5 changes: 5 additions & 0 deletions llvm/lib/Target/AMDGPU/AMDGPU.td
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Expand Up @@ -2115,6 +2115,11 @@ def FeatureISAVersion12_Generic: FeatureSet<

def AMDGPUInstrInfo : InstrInfo {
let guessInstructionProperties = 1;
let CoalesceDecoderNamespaces = [
["GFX11", "GFX11_FAKE16"],
["GFX12", "GFX12_FAKE16"],
["GFX1250", "GFX1250_FAKE16"],
];
}

def AMDGPUAsmParser : AsmParser {
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31 changes: 9 additions & 22 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Expand Up @@ -617,18 +617,15 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
std::bitset<96> DecW = eat12Bytes(Bytes);

if (isGFX11() &&
tryDecodeInst(DecoderTableGFX1196, DecoderTableGFX11_FAKE1696, MI,
DecW, Address, CS))
tryDecodeInst(DecoderTableGFX1196, MI, DecW, Address, CS))
break;

if (isGFX1250() &&
tryDecodeInst(DecoderTableGFX125096, DecoderTableGFX1250_FAKE1696, MI,
DecW, Address, CS))
tryDecodeInst(DecoderTableGFX125096, MI, DecW, Address, CS))
break;

if (isGFX12() &&
tryDecodeInst(DecoderTableGFX1296, DecoderTableGFX12_FAKE1696, MI,
DecW, Address, CS))
tryDecodeInst(DecoderTableGFX1296, MI, DecW, Address, CS))
break;

if (isGFX12() &&
Expand Down Expand Up @@ -698,18 +695,13 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
break;

if (isGFX1250() &&
tryDecodeInst(DecoderTableGFX125064, DecoderTableGFX1250_FAKE1664, MI,
QW, Address, CS))
tryDecodeInst(DecoderTableGFX125064, MI, QW, Address, CS))
break;

if (isGFX12() &&
tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW,
Address, CS))
if (isGFX12() && tryDecodeInst(DecoderTableGFX1264, MI, QW, Address, CS))
break;

if (isGFX11() &&
tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
Address, CS))
if (isGFX11() && tryDecodeInst(DecoderTableGFX1164, MI, QW, Address, CS))
break;

if (isGFX11() &&
Expand Down Expand Up @@ -753,19 +745,14 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
if (isGFX10() && tryDecodeInst(DecoderTableGFX1032, MI, DW, Address, CS))
break;

if (isGFX11() &&
tryDecodeInst(DecoderTableGFX1132, DecoderTableGFX11_FAKE1632, MI, DW,
Address, CS))
if (isGFX11() && tryDecodeInst(DecoderTableGFX1132, MI, DW, Address, CS))
break;

if (isGFX1250() &&
tryDecodeInst(DecoderTableGFX125032, DecoderTableGFX1250_FAKE1632, MI,
DW, Address, CS))
tryDecodeInst(DecoderTableGFX125032, MI, DW, Address, CS))
break;

if (isGFX12() &&
tryDecodeInst(DecoderTableGFX1232, DecoderTableGFX12_FAKE1632, MI, DW,
Address, CS))
if (isGFX12() && tryDecodeInst(DecoderTableGFX1232, MI, DW, Address, CS))
break;
}

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8 changes: 4 additions & 4 deletions llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
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Expand Up @@ -691,9 +691,9 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
// Standard Extensions
{DecoderTable32, {}, "standard 32-bit instructions"},
{DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
{DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
{DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
//{DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
//{DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
//{DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
};

namespace {
Expand Down Expand Up @@ -743,7 +743,7 @@ static constexpr DecoderListEntry DecoderList16[]{
// DecoderTableZicfiss16 must be checked before DecoderTable16.
{DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
{DecoderTable16, {}, "standard 16-bit instructions"},
{DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
//{DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
// Zc* instructions incompatible with Zcf or Zcd
{DecoderTableZcOverlap16,
{},
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5 changes: 5 additions & 0 deletions llvm/lib/Target/RISCV/RISCV.td
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Expand Up @@ -85,6 +85,11 @@ include "RISCVPfmCounters.td"

def RISCVInstrInfo : InstrInfo {
let guessInstructionProperties = 0;
let CoalesceDecoderNamespaces = [
["", "RV32Only", "Zfinx", "ZdinxRV32Only"]
// ["Zicfiss", "", "RV32Only", "ZcOverlap"], // Need to handle RV32Only mappings.
];

}

def RISCVAsmParser : AsmParser {
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8 changes: 4 additions & 4 deletions llvm/test/TableGen/FixedLenDecoderEmitter/additional-encoding.td
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Expand Up @@ -31,22 +31,22 @@ class I<dag out_ops, dag in_ops> : Instruction {
}

// CHECK: /* 0 */ MCD::OPC_ExtractField, 12, 4, // Inst{15-12} ...
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 0, 15, 0, // Skip to: 22
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 0, 15, 0, // FilterVal = 0x0, Skip to: 22
// CHECK-NEXT: /* 7 */ MCD::OPC_Scope, 8, 0, // Skip to: 18
// CHECK-NEXT: /* 10 */ MCD::OPC_CheckField, 6, 6, 0,
// CHECK-NEXT: /* 14 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
// CHECK-NEXT: /* 18 */ MCD::OPC_TryDecode, 187, 2, 1,
// CHECK-NEXT: /* 22 */ MCD::OPC_FilterValueOrSkip, 1, 15, 0, // Skip to: 41
// CHECK-NEXT: /* 22 */ MCD::OPC_FilterValueOrSkip, 1, 15, 0, // FilterVal = 0x1, Skip to: 41
// CHECK-NEXT: /* 26 */ MCD::OPC_Scope, 8, 0, // Skip to: 37
// CHECK-NEXT: /* 29 */ MCD::OPC_CheckField, 6, 6, 0,
// CHECK-NEXT: /* 33 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
// CHECK-NEXT: /* 37 */ MCD::OPC_TryDecode, 188, 2, 1,
// CHECK-NEXT: /* 41 */ MCD::OPC_FilterValueOrSkip, 2, 15, 0, // Skip to: 60
// CHECK-NEXT: /* 41 */ MCD::OPC_FilterValueOrSkip, 2, 15, 0, // FilterVal = 0x2, Skip to: 60
// CHECK-NEXT: /* 45 */ MCD::OPC_Scope, 8, 0, // Skip to: 56
// CHECK-NEXT: /* 48 */ MCD::OPC_CheckField, 6, 6, 0,
// CHECK-NEXT: /* 52 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
// CHECK-NEXT: /* 56 */ MCD::OPC_TryDecode, 189, 2, 1,
// CHECK-NEXT: /* 60 */ MCD::OPC_FilterValue, 3,
// CHECK-NEXT: /* 60 */ MCD::OPC_FilterValue, 3, // FilterVal = 0x3
// CHECK-NEXT: /* 62 */ MCD::OPC_Scope, 8, 0, // Skip to: 73
// CHECK-NEXT: /* 65 */ MCD::OPC_CheckField, 6, 6, 0,
// CHECK-NEXT: /* 69 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: {{.*}}:NOP, DecodeIdx: 0
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4 changes: 2 additions & 2 deletions llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td
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Expand Up @@ -13,10 +13,10 @@ class I : Instruction {
//
// CHECK-LABEL: static const uint8_t DecoderTable128[34] = {
// CHECK-NEXT: /* 0 */ MCD::OPC_ExtractField, 0, 64, // Inst{63-0} ...
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 1, 8, 0, // Skip to: 15
// CHECK-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 1, 8, 0, // FilterVal = 0x1, Skip to: 15
// CHECK-NEXT: /* 7 */ MCD::OPC_CheckField, 127, 1, 1,
// CHECK-NEXT: /* 11 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I2, DecodeIdx: 0
// CHECK-NEXT: /* 15 */ MCD::OPC_FilterValue, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1,
// CHECK-NEXT: /* 15 */ MCD::OPC_FilterValue, 255, 255, 255, 255, 255, 255, 255, 255, 255, 1, // FilterVal = 0xffffffffffffffff
// CHECK-NEXT: /* 26 */ MCD::OPC_CheckField, 127, 1, 0,
// CHECK-NEXT: /* 30 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I1, DecodeIdx: 0
// CHECK-NEXT: };
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31 changes: 24 additions & 7 deletions llvm/test/TableGen/FixedLenDecoderEmitter/conflict.td
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Expand Up @@ -9,27 +9,44 @@ def MyTarget : Target { let InstructionSet = MyTargetISA; }
def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;

def X0 : Register<"x0"> { let Namespace = "MyTarget"; }
def GPR64 : RegisterClass<"MyTarget", [i64], 64, (add X0)>;

class I<dag OOps, dag IOps, list<dag> Pat>
: Instruction {
let Namespace = "MyTarget";
let OutOperandList = OOps;
let InOperandList = IOps;
let Pattern = Pat;
let Size = 4;
bits<32> Inst;
bits<32> SoftFail;
}

// Assume there isa 2 bit encoding for the dst and src register.
def A : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
let Size = 4;
let Inst{31...0} = 0;
bits<2> dst;
bits<2> src1;
let Inst{31...4} = 0;
let Inst{1...0} = dst;
let Inst{3...2} = src1;
}

def B : I<(outs GPR32:$dst), (ins GPR32:$src1), []> {
let Size = 4;
let Inst{31...0} = 0;
bits<2> dst;
bits<2> src1;
let Inst{31...4} = 0;
let Inst{1...0} = dst;
let Inst{3...2} = src1;
}

def C : I<(outs), (ins), []> {
let Inst{31...4} = 1;
let Inst{3...0} = 0;
}

// CHECK: Decoding Conflict:
// CHECK: ................................
// CHECK: 00000000000000000000000000000000
// CHECK: 00000000000000000000000000000000 A
// CHECK: 00000000000000000000000000000000 B
// CHECK: 0000000000000000000000000000....
// CHECK: 0000000000000000000000000000____ A
// CHECK: 0000000000000000000000000000____ B
10 changes: 5 additions & 5 deletions llvm/test/TableGen/FixedLenDecoderEmitter/var-len-conflict-1.td
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Expand Up @@ -20,16 +20,16 @@ class I : Instruction {

// CHECK: /* 0 */ MCD::OPC_Scope, 17, 0, // Skip to: 20
// CHECK-NEXT: /* 3 */ MCD::OPC_ExtractField, 0, 1, // Inst{0} ...
// CHECK-NEXT: /* 6 */ MCD::OPC_FilterValueOrSkip, 0, 4, 0, // Skip to: 14
// CHECK-NEXT: /* 6 */ MCD::OPC_FilterValueOrSkip, 0, 4, 0, // FilterVal = 0x0, Skip to: 14
// CHECK-NEXT: /* 10 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I8_0, DecodeIdx: 0
// CHECK-NEXT: /* 14 */ MCD::OPC_FilterValue, 1,
// CHECK-NEXT: /* 14 */ MCD::OPC_FilterValue, 1, // FilterVal = 0x1
// CHECK-NEXT: /* 16 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 0, // Opcode: I8_1, DecodeIdx: 0
// CHECK-NEXT: /* 20 */ MCD::OPC_ExtractField, 8, 8, // Inst{15-8} ...
// CHECK-NEXT: /* 23 */ MCD::OPC_FilterValueOrSkip, 0, 4, 0, // Skip to: 31
// CHECK-NEXT: /* 23 */ MCD::OPC_FilterValueOrSkip, 0, 4, 0, // FilterVal = 0x0, Skip to: 31
// CHECK-NEXT: /* 27 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_0, DecodeIdx: 1
// CHECK-NEXT: /* 31 */ MCD::OPC_FilterValueOrSkip, 1, 4, 0, // Skip to: 39
// CHECK-NEXT: /* 31 */ MCD::OPC_FilterValueOrSkip, 1, 4, 0, // FilterVal = 0x1, Skip to: 39
// CHECK-NEXT: /* 35 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_1, DecodeIdx: 1
// CHECK-NEXT: /* 39 */ MCD::OPC_FilterValue, 2,
// CHECK-NEXT: /* 39 */ MCD::OPC_FilterValue, 2, // FilterVal = 0x2
// CHECK-NEXT: /* 41 */ MCD::OPC_Decode, {{[0-9]+}}, 2, 1, // Opcode: I16_2, DecodeIdx: 1

def I8_0 : I { dag Inst = (descend (operand "$op", 7), 0b0); }
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8 changes: 4 additions & 4 deletions llvm/test/TableGen/VarLenDecoder.td
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Expand Up @@ -54,16 +54,16 @@ def FOO32 : MyVarInst<MemOp32> {
// CHECK-NEXT: };

// CHECK-SMALL: /* 0 */ MCD::OPC_ExtractField, 3, 5, // Inst{7-3} ...
// CHECK-SMALL-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 8, 4, 0, // Skip to: 11
// CHECK-SMALL-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 8, 4, 0, // FilterVal = 0x8, Skip to: 11
// CHECK-SMALL-NEXT: /* 7 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 0, // Opcode: FOO16
// CHECK-SMALL-NEXT: /* 11 */ MCD::OPC_FilterValue, 9,
// CHECK-SMALL-NEXT: /* 11 */ MCD::OPC_FilterValue, 9, // FilterVal = 0x9
// CHECK-SMALL-NEXT: /* 13 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: FOO32
// CHECK-SMALL-NEXT: };

// CHECK-LARGE: /* 0 */ MCD::OPC_ExtractField, 3, 5, // Inst{7-3} ...
// CHECK-LARGE-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 8, 4, 0, 0, // Skip to: 12
// CHECK-LARGE-NEXT: /* 3 */ MCD::OPC_FilterValueOrSkip, 8, 4, 0, 0, // FilterVal = 0x8, Skip to: 12
// CHECK-LARGE-NEXT: /* 8 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 0, // Opcode: FOO16
// CHECK-LARGE-NEXT: /* 12 */ MCD::OPC_FilterValue, 9,
// CHECK-LARGE-NEXT: /* 12 */ MCD::OPC_FilterValue, 9, // FilterVal = 0x9
// CHECK-LARGE-NEXT: /* 14 */ MCD::OPC_Decode, {{[0-9]+}}, {{[0-9]+}}, 1, // Opcode: FOO32
// CHECK-LARGE-NEXT: };

Expand Down
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