Skip to content

[InstCombine] Enable FAdd simplifications when user can ignore sign bit #157757

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 6 commits into from
Sep 12, 2025
+57 −0
Merged

[InstCombine] Enable FAdd simplifications when user can ignore sign bit #157757

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
6 commits
Select commit Hold shift + click to select a range
b230ed7
[InstSimplify] Enable FAdd simplifications when user can ignore sign bit
VedantParanjape Sep 9, 2025
3aaf155
moved opt to IC from InstSimplify
VedantParanjape Sep 10, 2025
717c2c8
revert fcanonicalize testcase
VedantParanjape Sep 10, 2025
486bbe7
rework to check for a single use, and update the testcase
VedantParanjape Sep 11, 2025
9ff60ee
Add support for FSub as well
VedantParanjape Sep 11, 2025
1dd1c85
Update llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
VedantParanjape Sep 12, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
20 changes: 20 additions & 0 deletions llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2002,6 +2002,16 @@ Instruction *InstCombinerImpl::visitFAdd(BinaryOperator &I) {
if (Instruction *FoldedFAdd = foldBinOpIntoSelectOrPhi(I))
return FoldedFAdd;

// B = fadd A, 0.0
// Z = Op B
// can be transformed into
// Z = Op A
// Where Op is such that we can ignore sign of 0 in fadd
Value *A;
if (match(&I, m_OneUse(m_FAdd(m_Value(A), m_AnyZeroFP()))) &&
canIgnoreSignBitOfZero(*I.use_begin()))
return replaceInstUsesWith(I, A);

// (-X) + Y --> Y - X
Value *X, *Y;
if (match(&I, m_c_FAdd(m_FNeg(m_Value(X)), m_Value(Y))))
Expand Down Expand Up @@ -3115,6 +3125,16 @@ Instruction *InstCombinerImpl::visitFSub(BinaryOperator &I) {
Value *X, *Y;
Constant *C;

// B = fsub A, 0.0
// Z = Op B
// can be transformed into
// Z = Op A
// Where Op is such that we can ignore sign of 0 in fsub
Value *A;
if (match(&I, m_OneUse(m_FSub(m_Value(A), m_AnyZeroFP()))) &&
canIgnoreSignBitOfZero(*I.use_begin()))
return replaceInstUsesWith(I, A);
Copy link
Contributor

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

This fold doesn't make sense, as fsub x, C will be canonicalized to fadd x, -C. The test case you added makes even less sense because it uses fsub x, 0.0 aka fadd x, -0.0 which is always a no-op and does not actually depend on the use-based logic.

Please remove this code again.


Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
// If Op0 is not -0.0 or we can ignore -0.0: Z - (X - Y) --> Z + (Y - X)
// Canonicalize to fadd to make analysis easier.
Expand Down
37 changes: 37 additions & 0 deletions llvm/test/Transforms/InstCombine/fold-fadd-with-zero-gh154238.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,37 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -passes=instcombine -S | FileCheck %s
define float @src(float %arg1) {
; CHECK-LABEL: define float @src(
; CHECK-SAME: float [[ARG1:%.*]]) {
; CHECK-NEXT: [[V3:%.*]] = call float @llvm.fabs.f32(float [[ARG1]])
; CHECK-NEXT: ret float [[V3]]
;
%v2 = fadd float %arg1, 0.000000e+00
%v3 = call float @llvm.fabs.f32(float %v2)
ret float %v3
}

define float @src2(float %arg1) {
; CHECK-LABEL: define float @src2(
; CHECK-SAME: float [[ARG1:%.*]]) {
; CHECK-NEXT: [[V2:%.*]] = fadd float [[ARG1]], 0.000000e+00
; CHECK-NEXT: [[V3:%.*]] = call float @llvm.fabs.f32(float [[V2]])
; CHECK-NEXT: [[V4:%.*]] = fsub float [[V2]], [[V3]]
; CHECK-NEXT: ret float [[V4]]
;
%v2 = fadd float %arg1, 0.000000e+00
%v3 = call float @llvm.fabs.f32(float %v2)
%v4 = fsub float %v2, %v3
ret float %v4
}

define float @src_sub(float %arg1) {
; CHECK-LABEL: define float @src_sub(
; CHECK-SAME: float [[ARG1:%.*]]) {
; CHECK-NEXT: [[V3:%.*]] = call float @llvm.fabs.f32(float [[ARG1]])
; CHECK-NEXT: ret float [[V3]]
;
%v2 = fsub float %arg1, 0.000000e+00
%v3 = call float @llvm.fabs.f32(float %v2)
ret float %v3
}