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[ARM] Allow s constraints on half #157860

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Merged
merged 1 commit into from
Sep 11, 2025
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[ARM] Allow s constraints on half #157860

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8 changes: 5 additions & 3 deletions llvm/lib/Target/ARM/ARMISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -20304,9 +20304,11 @@ ARMTargetLowering::getSingleConstraintMatchWeight(
static bool isIncompatibleReg(const MCPhysReg &PR, MVT VT) {
if (PR == 0 || VT == MVT::Other)
return false;
return (ARM::SPRRegClass.contains(PR) && VT != MVT::f32 && VT != MVT::i32) ||
(ARM::DPRRegClass.contains(PR) && VT != MVT::f64 &&
!VT.is64BitVector());
if (ARM::SPRRegClass.contains(PR))
return VT != MVT::f32 && VT != MVT::f16 && VT != MVT::i32;
if (ARM::DPRRegClass.contains(PR))
return VT != MVT::f64 && !VT.is64BitVector();
return false;
}

using RCPair = std::pair<unsigned, const TargetRegisterClass *>;
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77 changes: 77 additions & 0 deletions llvm/test/CodeGen/ARM/inlineasm-fp-half.ll
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Expand Up @@ -495,3 +495,80 @@ entry:
%0 = tail call bfloat asm "vmov $0, $1", "=x,x"(bfloat %x)
ret bfloat %0
}

define half @half_s(half %x) nounwind {
; NO-FP16-SOFTFP-LABEL: half_s:
; NO-FP16-SOFTFP: @ %bb.0: @ %entry
; NO-FP16-SOFTFP-NEXT: vmov s2, r0
; NO-FP16-SOFTFP-NEXT: @APP
; NO-FP16-SOFTFP-NEXT: vmov.f32 s1, s2
; NO-FP16-SOFTFP-NEXT: @NO_APP
; NO-FP16-SOFTFP-NEXT: vmov r0, s1
; NO-FP16-SOFTFP-NEXT: bx lr
;
; NO-FP16-HARD-LABEL: half_s:
; NO-FP16-HARD: @ %bb.0: @ %entry
; NO-FP16-HARD-NEXT: vmov.f32 s2, s0
; NO-FP16-HARD-NEXT: @APP
; NO-FP16-HARD-NEXT: vmov.f32 s1, s2
; NO-FP16-HARD-NEXT: @NO_APP
; NO-FP16-HARD-NEXT: vmov.f32 s0, s1
; NO-FP16-HARD-NEXT: bx lr
;
; FP16-SOFTFP-LABEL: half_s:
; FP16-SOFTFP: @ %bb.0: @ %entry
; FP16-SOFTFP-NEXT: vmov.f16 s2, r0
; FP16-SOFTFP-NEXT: @APP
; FP16-SOFTFP-NEXT: vmov.f32 s1, s2
; FP16-SOFTFP-NEXT: @NO_APP
; FP16-SOFTFP-NEXT: vmov r0, s1
; FP16-SOFTFP-NEXT: bx lr
;
; FP16-HARD-LABEL: half_s:
; FP16-HARD: @ %bb.0: @ %entry
; FP16-HARD-NEXT: vmov.f32 s2, s0
; FP16-HARD-NEXT: @APP
; FP16-HARD-NEXT: vmov.f32 s1, s2
; FP16-HARD-NEXT: @NO_APP
; FP16-HARD-NEXT: vmov.f32 s0, s1
; FP16-HARD-NEXT: bx lr
;
; BF16-SOFTFP-LABEL: half_s:
; BF16-SOFTFP: @ %bb.0: @ %entry
; BF16-SOFTFP-NEXT: vmov.f16 s2, r0
; BF16-SOFTFP-NEXT: @APP
; BF16-SOFTFP-NEXT: vmov.f32 s1, s2
; BF16-SOFTFP-NEXT: @NO_APP
; BF16-SOFTFP-NEXT: vmov r0, s1
; BF16-SOFTFP-NEXT: bx lr
;
; SIMD-BF16-SOFTFP-LABEL: half_s:
; SIMD-BF16-SOFTFP: @ %bb.0: @ %entry
; SIMD-BF16-SOFTFP-NEXT: vmov.f16 s2, r0
; SIMD-BF16-SOFTFP-NEXT: @APP
; SIMD-BF16-SOFTFP-NEXT: vmov.f32 s1, s2
; SIMD-BF16-SOFTFP-NEXT: @NO_APP
; SIMD-BF16-SOFTFP-NEXT: vmov r0, s1
; SIMD-BF16-SOFTFP-NEXT: bx lr
;
; BF16-HARD-LABEL: half_s:
; BF16-HARD: @ %bb.0: @ %entry
; BF16-HARD-NEXT: vmov.f32 s2, s0
; BF16-HARD-NEXT: @APP
; BF16-HARD-NEXT: vmov.f32 s1, s2
; BF16-HARD-NEXT: @NO_APP
; BF16-HARD-NEXT: vmov.f32 s0, s1
; BF16-HARD-NEXT: bx lr
;
; SIMD-BF16-HARD-LABEL: half_s:
; SIMD-BF16-HARD: @ %bb.0: @ %entry
; SIMD-BF16-HARD-NEXT: vmov.f32 s2, s0
; SIMD-BF16-HARD-NEXT: @APP
; SIMD-BF16-HARD-NEXT: vmov.f32 s1, s2
; SIMD-BF16-HARD-NEXT: @NO_APP
; SIMD-BF16-HARD-NEXT: vmov.f32 s0, s1
; SIMD-BF16-HARD-NEXT: bx lr
entry:
%0 = tail call half asm "vmov $0, $1", "={s1},{s2}"(half %x)
ret half %0
}