[PowerPC] Implement VSX Vector Integer Arithmetic Instructions

llvm/lib/Target/PowerPC/PPCInstrFuture.td

@@ -120,6 +120,31 @@ class VXForm_VRTAB5<bits<11> xo, dag OOL, dag IOL, string asmstr,
   let Inst{21...31} = xo;
 }
 
+class XX3Form_XTAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
+                    list<dag> pattern>
+    : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+
+  bits<6> XT;
+  bits<6> XA;
+  bits<6> XB;
+
+  let Pattern = pattern;
+
+  let Inst{6...10} = XT{4...0};
+  let Inst{11...15} = XA{4...0};
+  let Inst{16...20} = XB{4...0};
+  let Inst{21...28} = xo;
+  let Inst{29} = XA{5};
+  let Inst{30} = XB{5};
+  let Inst{31} = XT{5};
+}
+
+//-------------------------- Instruction definitions -------------------------//
+
+// Predicate combinations available:
+// [IsISAFuture]
+// [HasVSX, IsISAFuture]
+
 let Predicates = [IsISAFuture] in {
   defm SUBFUS : XOForm_RTAB5_L1r<31, 72, (outs g8rc:$RT),
                                  (ins g8rc:$RA, g8rc:$RB, u1imm:$L), "subfus",
@@ -191,4 +216,26 @@ let Predicates = [HasVSX, IsISAFuture] in {
   def VUCMPRLH
       : VXForm_VRTAB5<323, (outs vrrc:$VRT), (ins vrrc:$VRA, vrrc:$VRB),
                       "vucmprlh $VRT, $VRA, $VRB", []>;
+
+  // VSX Vector Integer Arithmetic Instructions
+  def XVADDUWM : XX3Form_XTAB6<60, 131, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                               "xvadduwm $XT, $XA, $XB", []>;
+  def XVADDUHM : XX3Form_XTAB6<60, 139, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                               "xvadduhm $XT, $XA, $XB", []>;
+  def XVSUBUWM: XX3Form_XTAB6<60, 147, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                              "xvsubuwm $XT, $XA, $XB", []>;
+  def XVSUBUHM: XX3Form_XTAB6<60, 155, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                              "xvsubuhm $XT, $XA, $XB", []>;
+  def XVMULUWM: XX3Form_XTAB6<60, 163, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                              "xvmuluwm $XT, $XA, $XB", []>;
+  def XVMULUHM: XX3Form_XTAB6<60, 171, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                              "xvmuluhm $XT, $XA, $XB", []>;
+  def XVMULHSW: XX3Form_XTAB6<60, 179, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                              "xvmulhsw $XT, $XA, $XB", []>;
+  def XVMULHSH: XX3Form_XTAB6<60, 187, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                              "xvmulhsh $XT, $XA, $XB", []>;
+  def XVMULHUW: XX3Form_XTAB6<60, 114, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                              "xvmulhuw $XT, $XA, $XB", []>;
+  def XVMULHUH: XX3Form_XTAB6<60, 122, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
+                              "xvmulhuh $XT, $XA, $XB", []>;
 }

llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt

@@ -231,3 +231,33 @@
 
 #CHECK: vucmprhh 1, 3, 6
 0x10,0x23,0x31,0x03
+
+#CHECK: xvadduwm  4, 5, 7
+0xf0,0x85,0x3c,0x18
+
+#CHECK: xvadduhm  4, 5, 7
+0xf0,0x85,0x3c,0x58
+
+#CHECK: xvsubuwm  4, 5, 7
+0xf0,0x85,0x3c,0x98
+
+#CHECK: xvsubuhm  4, 5, 7
+0xf0,0x85,0x3c,0xd8
+
+#CHECK: xvmuluwm  4, 5, 7
+0xf0,0x85,0x3d,0x18
+
+#CHECK: xvmuluhm  4, 5, 7
+0xf0,0x85,0x3d,0x58
+
+#CHECK: xvmulhsw  4, 5, 7
+0xf0,0x85,0x3d,0x98
+
+#CHECK: xvmulhsh  4, 5, 7
+0xf0,0x85,0x3d,0xd8
+
+#CHECK: xvmulhuw  4, 5, 7
+0xf0,0x85,0x3b,0x90
+
+#CHECK: xvmulhuh  4, 5, 7
+0xf0,0x85,0x3b,0xd0

llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt

@@ -225,3 +225,33 @@
 
 #CHECK: vucmprhh 1, 3, 6
 0x03,0x31,0x23,0x10
+
+#CHECK: xvadduwm  4, 5, 7
+0x18,0x3c,0x85,0xf0
+
+#CHECK: xvadduhm  4, 5, 7
+0x58,0x3c,0x85,0xf0
+
+#CHECK: xvsubuwm  4, 5, 7
+0x98,0x3c,0x85,0xf0
+
+#CHECK: xvsubuhm  4, 5, 7
+0xd8,0x3c,0x85,0xf0
+
+#CHECK: xvmuluwm  4, 5, 7
+0x18,0x3d,0x85,0xf0
+
+#CHECK: xvmuluhm  4, 5, 7
+0x58,0x3d,0x85,0xf0
+
+#CHECK: xvmulhsw  4, 5, 7
+0x98,0x3d,0x85,0xf0
+
+#CHECK: xvmulhsh  4, 5, 7
+0xd8,0x3d,0x85,0xf0
+
+#CHECK: xvmulhuw  4, 5, 7
+0x90,0x3b,0x85,0xf0
+
+#CHECK: xvmulhuh  4, 5, 7
+0xd0,0x3b,0x85,0xf0

llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s

@@ -330,3 +330,43 @@
            vucmprhh 1, 3, 6
 #CHECK-BE: vucmprhh 1, 3, 6               # encoding: [0x10,0x23,0x31,0x03]
 #CHECK-LE: vucmprhh 1, 3, 6               # encoding: [0x03,0x31,0x23,0x10]
+
+           xvadduwm 4, 5, 7
+#CHECK-BE: xvadduwm 4, 5, 7              # encoding: [0xf0,0x85,0x3c,0x18]
+#CHECK-LE: xvadduwm 4, 5, 7              # encoding: [0x18,0x3c,0x85,0xf0]
+
+           xvadduhm 4, 5, 7
+#CHECK-BE: xvadduhm 4, 5, 7              # encoding: [0xf0,0x85,0x3c,0x58]
+#CHECK-LE: xvadduhm 4, 5, 7              # encoding: [0x58,0x3c,0x85,0xf0]
+
+           xvsubuwm 4, 5, 7
+#CHECK-BE: xvsubuwm 4, 5, 7              # encoding: [0xf0,0x85,0x3c,0x98]
+#CHECK-LE: xvsubuwm 4, 5, 7              # encoding: [0x98,0x3c,0x85,0xf0]
+
+           xvsubuhm 4, 5, 7
+#CHECK-BE: xvsubuhm 4, 5, 7              # encoding: [0xf0,0x85,0x3c,0xd8]
+#CHECK-LE: xvsubuhm 4, 5, 7              # encoding: [0xd8,0x3c,0x85,0xf0]
+
+           xvmuluwm 4, 5, 7
+#CHECK-BE: xvmuluwm 4, 5, 7              # encoding: [0xf0,0x85,0x3d,0x18]
+#CHECK-LE: xvmuluwm 4, 5, 7              # encoding: [0x18,0x3d,0x85,0xf0]
+
+           xvmuluhm 4, 5, 7
+#CHECK-BE: xvmuluhm 4, 5, 7              # encoding: [0xf0,0x85,0x3d,0x58]
+#CHECK-LE: xvmuluhm 4, 5, 7              # encoding: [0x58,0x3d,0x85,0xf0]
+
+           xvmulhsw 4, 5, 7
+#CHECK-BE: xvmulhsw 4, 5, 7              # encoding: [0xf0,0x85,0x3d,0x98]
+#CHECK-LE: xvmulhsw 4, 5, 7              # encoding: [0x98,0x3d,0x85,0xf0]
+
+           xvmulhsh 4, 5, 7
+#CHECK-BE: xvmulhsh 4, 5, 7              # encoding: [0xf0,0x85,0x3d,0xd8]
+#CHECK-LE: xvmulhsh 4, 5, 7              # encoding: [0xd8,0x3d,0x85,0xf0]
+
+           xvmulhuw 4, 5, 7
+#CHECK-BE: xvmulhuw 4, 5, 7              # encoding: [0xf0,0x85,0x3b,0x90]
+#CHECK-LE: xvmulhuw 4, 5, 7              # encoding: [0x90,0x3b,0x85,0xf0]
+
+           xvmulhuh 4, 5, 7
+#CHECK-BE: xvmulhuh 4, 5, 7              # encoding: [0xf0,0x85,0x3b,0xd0]
+#CHECK-LE: xvmulhuh 4, 5, 7              # encoding: [0xd0,0x3b,0x85,0xf0]