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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3452,7 +3452,7 @@ bool SITargetLowering::CanLowerReturn(

// We must use the stack if return would require unavailable registers.
unsigned MaxNumVGPRs = Subtarget->getMaxNumVGPRs(MF);
unsigned TotalNumVGPRs = AMDGPU::VGPR_32RegClass.getNumRegs();
unsigned TotalNumVGPRs = Subtarget->getAddressableNumArchVGPRs();
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This use is curious, we should only be looking at the number of registers used for return in the calling convention

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I am not even saying it was correct. But using registers which do not exist is not correct for sure. It has just... floated to the top.

for (unsigned i = MaxNumVGPRs; i < TotalNumVGPRs; ++i)
if (CCInfo.isAllocated(AMDGPU::VGPR_32RegClass.getRegister(i)))
return false;
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2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -86,7 +86,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
// FIXME: MayNeedAGPRs is a misnomer for how this is used. MFMA selection
// should be separated from availability of AGPRs
if (MFMAVGPRForm ||
(ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
(ST.getMaxNumVGPRs(F) <= ST.getAddressableNumArchVGPRs() &&
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I'm working on deleting this part

!mayUseAGPRs(F)))
MayNeedAGPRs = false; // We will select all MAI with VGPR operands.
}
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9 changes: 6 additions & 3 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1399,13 +1399,16 @@ unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
return IsWave32 ? 1024 : 512;
}

unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI) { return 256; }
unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI) {
const auto &Features = STI->getFeatureBits();
if (Features.test(Feature1024AddressableVGPRs))
return Features.test(FeatureWavefrontSize32) ? 1024 : 512;
return 256;
}

unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI,
unsigned DynamicVGPRBlockSize) {
const auto &Features = STI->getFeatureBits();
if (Features.test(FeatureGFX1250Insts))
return Features.test(FeatureWavefrontSize32) ? 1024 : 512;
if (Features.test(FeatureGFX90AInsts))
return 512;

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