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Merged
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Sep 10, 2025
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Revert "[DAGCombiner] Relax condition for extract_vector_elt combine" #157953

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f47a89e
Revert "[DAGCombiner] Relax condition for extract_vector_elt combine …
aeubanks Sep 10, 2025
a5ed32a
Merge branch 'main' into revert-157658-users/zhaoqi5/relax-extractelt…
aeubanks Sep 10, 2025
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3 changes: 2 additions & 1 deletion llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Expand Up @@ -23933,7 +23933,8 @@ SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// scalar_to_vector here as well.

if (!LegalOperations ||
TLI.isOperationLegalOrCustom(ISD::EXTRACT_VECTOR_ELT, VecVT) ||
// FIXME: Should really be just isOperationLegalOrCustom.
TLI.isOperationLegal(ISD::EXTRACT_VECTOR_ELT, VecVT) ||
TLI.isOperationExpand(ISD::VECTOR_SHUFFLE, VecVT)) {
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ScalarVT, SVInVec,
DAG.getVectorIdxConstant(OrigElt, DL));
Expand Down
11 changes: 6 additions & 5 deletions llvm/test/CodeGen/AArch64/shufflevector.ll
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Expand Up @@ -286,11 +286,10 @@ define i32 @shufflevector_v2i16(<2 x i16> %a, <2 x i16> %b){
; CHECK-SD: // %bb.0:
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1
; CHECK-SD-NEXT: str h1, [sp, #14]
; CHECK-SD-NEXT: mov s0, v0.s[1]
; CHECK-SD-NEXT: ext v0.8b, v0.8b, v1.8b, #4
; CHECK-SD-NEXT: mov s1, v0.s[1]
; CHECK-SD-NEXT: str h0, [sp, #12]
; CHECK-SD-NEXT: str h1, [sp, #14]
; CHECK-SD-NEXT: ldr w0, [sp, #12]
; CHECK-SD-NEXT: add sp, sp, #16
; CHECK-SD-NEXT: ret
Expand Down Expand Up @@ -492,8 +491,10 @@ define i32 @shufflevector_v2i16_zeroes(<2 x i16> %a, <2 x i16> %b){
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
; CHECK-SD-NEXT: str h0, [sp, #14]
; CHECK-SD-NEXT: dup v1.2s, v0.s[0]
; CHECK-SD-NEXT: str h0, [sp, #12]
; CHECK-SD-NEXT: mov s1, v1.s[1]
; CHECK-SD-NEXT: str h1, [sp, #14]
; CHECK-SD-NEXT: ldr w0, [sp, #12]
; CHECK-SD-NEXT: add sp, sp, #16
; CHECK-SD-NEXT: ret
Expand Down
10 changes: 6 additions & 4 deletions llvm/test/CodeGen/Thumb2/active_lane_mask.ll
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Expand Up @@ -107,7 +107,6 @@ define <7 x i32> @v7i32(i32 %index, i32 %TC, <7 x i32> %V1, <7 x i32> %V2) {
; CHECK-NEXT: vstrw.32 q0, [r0]
; CHECK-NEXT: vldrw.u32 q0, [r2]
; CHECK-NEXT: ldr r2, [sp, #48]
; CHECK-NEXT: adds r0, #16
; CHECK-NEXT: vqadd.u32 q0, q0, r1
; CHECK-NEXT: ldr r1, [sp, #52]
; CHECK-NEXT: vcmp.u32 hi, q3, q0
Expand All @@ -120,9 +119,12 @@ define <7 x i32> @v7i32(i32 %index, i32 %TC, <7 x i32> %V1, <7 x i32> %V2) {
; CHECK-NEXT: ldr r1, [sp, #24]
; CHECK-NEXT: vmov q1[2], q1[0], r2, r1
; CHECK-NEXT: vpsel q0, q1, q0
; CHECK-NEXT: vmov r1, r2, d0
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: stm r0!, {r1, r2, r3}
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov r3, s0
; CHECK-NEXT: vmov r2, s2
; CHECK-NEXT: strd r3, r2, [r0, #16]
; CHECK-NEXT: str r1, [r0, #24]
; CHECK-NEXT: bx lr
; CHECK-NEXT: .p2align 4
; CHECK-NEXT: @ %bb.1:
Expand Down
29 changes: 17 additions & 12 deletions llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-i16-add.ll
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Expand Up @@ -31,19 +31,24 @@ entry:
define arm_aapcs_vfpcc <4 x i16> @complex_add_v4i16(<4 x i16> %a, <4 x i16> %b) {
; CHECK-LABEL: complex_add_v4i16:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: vmov r12, r1, d1
; CHECK-NEXT: vmov r2, lr, d3
; CHECK-NEXT: vmov r3, r4, d2
; CHECK-NEXT: vrev64.32 q2, q0
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: vrev64.32 q3, q1
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: subs r0, r1, r0
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: subs r1, r2, r1
; CHECK-NEXT: vmov r2, r0, d0
; CHECK-NEXT: subs r0, r3, r0
; CHECK-NEXT: vmov q0[2], q0[0], r0, r1
; CHECK-NEXT: add.w r0, lr, r12
; CHECK-NEXT: adds r1, r4, r2
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: add r0, r1
; CHECK-NEXT: vmov r1, s12
; CHECK-NEXT: add r1, r2
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%a.real = shufflevector <4 x i16> %a, <4 x i16> zeroinitializer, <2 x i32> <i32 0, i32 2>
%a.imag = shufflevector <4 x i16> %a, <4 x i16> zeroinitializer, <2 x i32> <i32 1, i32 3>
Expand Down
29 changes: 17 additions & 12 deletions llvm/test/CodeGen/Thumb2/mve-complex-deinterleaving-i8-add.ll
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Expand Up @@ -31,19 +31,24 @@ entry:
define arm_aapcs_vfpcc <4 x i8> @complex_add_v4i8(<4 x i8> %a, <4 x i8> %b) {
; CHECK-LABEL: complex_add_v4i8:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: vmov r12, r1, d1
; CHECK-NEXT: vmov r2, lr, d3
; CHECK-NEXT: vmov r3, r4, d2
; CHECK-NEXT: vrev64.32 q2, q0
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: vmov r0, s10
; CHECK-NEXT: vrev64.32 q3, q1
; CHECK-NEXT: vmov r2, s4
; CHECK-NEXT: subs r0, r1, r0
; CHECK-NEXT: vmov r1, s8
; CHECK-NEXT: subs r1, r2, r1
; CHECK-NEXT: vmov r2, r0, d0
; CHECK-NEXT: subs r0, r3, r0
; CHECK-NEXT: vmov q0[2], q0[0], r0, r1
; CHECK-NEXT: add.w r0, lr, r12
; CHECK-NEXT: adds r1, r4, r2
; CHECK-NEXT: vmov q0[3], q0[1], r1, r0
; CHECK-NEXT: pop {r4, pc}
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: vmov q2[2], q2[0], r1, r0
; CHECK-NEXT: vmov r0, s14
; CHECK-NEXT: vmov r1, s2
; CHECK-NEXT: add r0, r1
; CHECK-NEXT: vmov r1, s12
; CHECK-NEXT: add r1, r2
; CHECK-NEXT: vmov q2[3], q2[1], r1, r0
; CHECK-NEXT: vmov q0, q2
; CHECK-NEXT: bx lr
entry:
%a.real = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <2 x i32> <i32 0, i32 2>
%a.imag = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <2 x i32> <i32 1, i32 3>
Expand Down
15 changes: 9 additions & 6 deletions llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
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Expand Up @@ -185,10 +185,11 @@ define arm_aapcs_vfpcc <6 x i32> @test_signed_v6f32_v6i32(<6 x float> %f) {
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov r1, r2, d2
; CHECK-MVEFP-NEXT: str r2, [r0, #20]
; CHECK-MVEFP-NEXT: vmov.f32 s6, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r1, s6
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: str r1, [r0, #16]
; CHECK-MVEFP-NEXT: bx lr
%x = call <6 x i32> @llvm.fptosi.sat.v6f32.v6i32(<6 x float> %f)
ret <6 x i32> %x
Expand Down Expand Up @@ -220,11 +221,13 @@ define arm_aapcs_vfpcc <7 x i32> @test_signed_v7f32_v7i32(<7 x float> %f) {
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.s32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov.f32 s10, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r3, s6
; CHECK-MVEFP-NEXT: vmov r1, r2, d2
; CHECK-MVEFP-NEXT: strd r2, r3, [r0, #20]
; CHECK-MVEFP-NEXT: vmov r1, s10
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: str r3, [r0, #24]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: str r1, [r0, #16]
; CHECK-MVEFP-NEXT: bx lr
%x = call <7 x i32> @llvm.fptosi.sat.v7f32.v7i32(<7 x float> %f)
ret <7 x i32> %x
Expand Down
15 changes: 9 additions & 6 deletions llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
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Expand Up @@ -172,10 +172,11 @@ define arm_aapcs_vfpcc <6 x i32> @test_unsigned_v6f32_v6i32(<6 x float> %f) {
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov r1, r2, d2
; CHECK-MVEFP-NEXT: str r2, [r0, #20]
; CHECK-MVEFP-NEXT: vmov.f32 s6, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r1, s6
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: str r1, [r0, #16]
; CHECK-MVEFP-NEXT: bx lr
%x = call <6 x i32> @llvm.fptoui.sat.v6f32.v6i32(<6 x float> %f)
ret <6 x i32> %x
Expand Down Expand Up @@ -207,11 +208,13 @@ define arm_aapcs_vfpcc <7 x i32> @test_unsigned_v7f32_v7i32(<7 x float> %f) {
; CHECK-MVEFP: @ %bb.0:
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q1, q1
; CHECK-MVEFP-NEXT: vcvt.u32.f32 q0, q0
; CHECK-MVEFP-NEXT: vmov.f32 s10, s5
; CHECK-MVEFP-NEXT: vmov r2, s4
; CHECK-MVEFP-NEXT: vmov r3, s6
; CHECK-MVEFP-NEXT: vmov r1, r2, d2
; CHECK-MVEFP-NEXT: strd r2, r3, [r0, #20]
; CHECK-MVEFP-NEXT: vmov r1, s10
; CHECK-MVEFP-NEXT: strd r2, r1, [r0, #16]
; CHECK-MVEFP-NEXT: str r3, [r0, #24]
; CHECK-MVEFP-NEXT: vstrw.32 q0, [r0]
; CHECK-MVEFP-NEXT: str r1, [r0, #16]
; CHECK-MVEFP-NEXT: bx lr
%x = call <7 x i32> @llvm.fptoui.sat.v7f32.v7i32(<7 x float> %f)
ret <7 x i32> %x
Expand Down
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