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[RISCV] Use default promotion for i32 CTLZ on RV64 with XTHeadBb. #157994

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Merged
merged 1 commit into from
Sep 11, 2025
Merged

[RISCV] Use default promotion for i32 CTLZ on RV64 with XTHeadBb. #157994

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9 changes: 3 additions & 6 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -421,12 +421,9 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
(Subtarget.hasVendorXCVbitmanip() && !Subtarget.is64Bit())) {
// We need the custom lowering to make sure that the resulting sequence
// for the 32bit case is efficient on 64bit targets.
if (Subtarget.is64Bit()) {
setOperationAction(ISD::CTLZ, MVT::i32, Custom);
// Use default promotion for XTHeadBb.
if (Subtarget.hasStdExtZbb())
setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Custom);
}
// Use default promotion for i32 without Zbb.
if (Subtarget.is64Bit() && Subtarget.hasStdExtZbb())
setOperationAction({ISD::CTLZ, ISD::CTLZ_ZERO_UNDEF}, MVT::i32, Custom);
} else {
setOperationAction(ISD::CTLZ, XLenVT, Expand);
}
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2 changes: 0 additions & 2 deletions llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
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Expand Up @@ -594,8 +594,6 @@ def : Pat<(i64 (sra (bswap GPR:$rs1), (i64 32))),
(TH_REVW GPR:$rs1)>;
def : Pat<(binop_allwusers<srl> (bswap GPR:$rs1), (i64 32)),
(TH_REVW GPR:$rs1)>;
def : Pat<(riscv_clzw GPR:$rs1),
(TH_FF0 (i64 (SLLI (i64 (XORI GPR:$rs1, -1)), 32)))>;
} // Predicates = [HasVendorXTHeadBb, IsRV64]

let Predicates = [HasVendorXTHeadBs] in {
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6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
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Expand Up @@ -1375,9 +1375,9 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
;
; RV64XTHEADBB-LABEL: test_ctlz_i32:
; RV64XTHEADBB: # %bb.0:
; RV64XTHEADBB-NEXT: not a0, a0
; RV64XTHEADBB-NEXT: slli a0, a0, 32
; RV64XTHEADBB-NEXT: th.ff0 a0, a0
; RV64XTHEADBB-NEXT: th.extu a0, a0, 31, 0
; RV64XTHEADBB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NEXT: addi a0, a0, -32
; RV64XTHEADBB-NEXT: ret
%tmp = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
ret i32 %tmp
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25 changes: 11 additions & 14 deletions llvm/test/CodeGen/RISCV/rv64xtheadbb.ll
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Expand Up @@ -52,9 +52,9 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
;
; RV64XTHEADBB-NOB-LABEL: ctlz_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: not a0, a0
; RV64XTHEADBB-NOB-NEXT: slli a0, a0, 32
; RV64XTHEADBB-NOB-NEXT: th.ff0 a0, a0
; RV64XTHEADBB-NOB-NEXT: th.extu a0, a0, 31, 0
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: addi a0, a0, -32
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: ctlz_i32:
Expand Down Expand Up @@ -112,10 +112,9 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
;
; RV64XTHEADBB-NOB-LABEL: log2_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: not a0, a0
; RV64XTHEADBB-NOB-NEXT: slli a0, a0, 32
; RV64XTHEADBB-NOB-NEXT: th.ff0 a0, a0
; RV64XTHEADBB-NOB-NEXT: li a1, 31
; RV64XTHEADBB-NOB-NEXT: th.extu a0, a0, 31, 0
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: li a1, 63
; RV64XTHEADBB-NOB-NEXT: sub a0, a1, a0
; RV64XTHEADBB-NOB-NEXT: ret
;
Expand Down Expand Up @@ -177,10 +176,9 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64XTHEADBB-NOB-LABEL: log2_ceil_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: addi a0, a0, -1
; RV64XTHEADBB-NOB-NEXT: not a0, a0
; RV64XTHEADBB-NOB-NEXT: slli a0, a0, 32
; RV64XTHEADBB-NOB-NEXT: th.ff0 a0, a0
; RV64XTHEADBB-NOB-NEXT: li a1, 32
; RV64XTHEADBB-NOB-NEXT: th.extu a0, a0, 31, 0
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: li a1, 64
; RV64XTHEADBB-NOB-NEXT: sub a0, a1, a0
; RV64XTHEADBB-NOB-NEXT: ret
;
Expand Down Expand Up @@ -309,9 +307,8 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64XTHEADBB-NOB-LABEL: ctlz_lshr_i32:
; RV64XTHEADBB-NOB: # %bb.0:
; RV64XTHEADBB-NOB-NEXT: srliw a0, a0, 1
; RV64XTHEADBB-NOB-NEXT: not a0, a0
; RV64XTHEADBB-NOB-NEXT: slli a0, a0, 32
; RV64XTHEADBB-NOB-NEXT: th.ff0 a0, a0
; RV64XTHEADBB-NOB-NEXT: th.ff1 a0, a0
; RV64XTHEADBB-NOB-NEXT: addi a0, a0, -32
; RV64XTHEADBB-NOB-NEXT: ret
;
; RV64XTHEADBB-B-LABEL: ctlz_lshr_i32:
Expand Down