Skip to content

AMDGPU: Use RegisterOperand for MIMG vaddr classes #158087

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 1 commit into from
Sep 11, 2025
Merged

AMDGPU: Use RegisterOperand for MIMG vaddr classes #158087

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
114 changes: 58 additions & 56 deletions llvm/lib/Target/AMDGPU/MIMGInstructions.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -272,13 +272,13 @@ class MIMGNSAHelper<int num_addrs,
!if(!le(num_addrs, 13), 3, ?))));
}

class PartialNSAHelper<int num_addrs, int max_addr, RegisterClass LastAddrRC>
class PartialNSAHelper<int num_addrs, int max_addr, RegisterOperand LastAddrRC>
: NSAHelper<> {

list<RegisterClass> addr_types =
list<RegisterOperand> addr_types =
!if(!ge(num_addrs, max_addr),
!listconcat(!listsplat(VGPR_32, !sub(max_addr, 1)), [LastAddrRC]),
!listsplat(VGPR_32, num_addrs));
!listconcat(!listsplat(VGPROp_32, !sub(max_addr, 1)), [LastAddrRC]),
!listsplat(VGPROp_32, num_addrs));

int VAddrCount = !if(!gt(num_addrs, max_addr), max_addr, num_addrs);
list<string> AddrAsmNames = !foreach(i, !range(VAddrCount), "vaddr" # i);
Expand Down Expand Up @@ -359,7 +359,7 @@ class MIMG_gfx11<int op, dag outs, string dns = "">
// Note that 1-dword addresses always use non-NSA variants.
class MIMG_nsa_gfx11<int op, dag outs, int num_addrs, string dns="",
list<RegisterClass> addr_types=[],
RegisterClass LastAddrRC = VGPR_32>
RegisterOperand LastAddrRC = VGPROp_32>
: MIMG<outs, dns>, MIMGe_gfx11<op> {
let SubtargetPredicate = isGFX11Only;
let AssemblerPredicate = isGFX11Only;
Expand Down Expand Up @@ -400,7 +400,7 @@ class VIMAGE_gfx12<int op, dag outs, int num_addrs, string dns="",
}

class VSAMPLE_gfx12<int op, dag outs, int num_addrs, string dns="",
RegisterClass Addr3RC>
RegisterOperand Addr3RC>
: VSAMPLE<outs, dns>, VSAMPLEe<op> {
let SubtargetPredicate = isGFX12Plus;
let AssemblerPredicate = isGFX12Plus;
Expand All @@ -421,7 +421,7 @@ class VSAMPLE_gfx12<int op, dag outs, int num_addrs, string dns="",

class MIMG_NoSampler_Helper <mimgopc op, string asm,
RegisterOperand dst_rc,
RegisterClass addr_rc,
RegisterOperand addr_rc,
string dns="">
: MIMG_gfx6789 <op.GFX10M, (outs dst_rc:$vdata), dns> {
let InOperandList = !con((ins addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
Expand All @@ -434,10 +434,10 @@ class MIMG_NoSampler_Helper <mimgopc op, string asm,

class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm,
RegisterOperand dst_rc,
RegisterClass addr_rc,
RegisterOperand addr_rc,
string dns="">
: MIMG_gfx90a <op.GFX10M, (outs getAlign2RegOp<dst_rc>.ret:$vdata), dns> {
let InOperandList = !con((ins addr_rc:$vaddr, SReg_256_XNULL:$srsrc,
let InOperandList = !con((ins getAlign2RegOp<addr_rc>.ret:$vaddr, SReg_256_XNULL:$srsrc,
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
R128A16:$r128, LWE:$lwe, DA:$da),
!if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
Expand All @@ -446,7 +446,7 @@ class MIMG_NoSampler_Helper_gfx90a <mimgopc op, string asm,
}

class MIMG_NoSampler_gfx10<mimgopc op, string opcode,
RegisterOperand DataRC, RegisterClass AddrRC,
RegisterOperand DataRC, RegisterOperand AddrRC,
string dns="">
: MIMG_gfx10<op.GFX10M, (outs DataRC:$vdata), dns> {
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
Expand All @@ -471,7 +471,7 @@ class MIMG_NoSampler_nsa_gfx10<mimgopc op, string opcode,
}

class MIMG_NoSampler_gfx11<mimgopc op, string opcode,
RegisterOperand DataRC, RegisterClass AddrRC,
RegisterOperand DataRC, RegisterOperand AddrRC,
string dns="">
: MIMG_gfx11<op.GFX11, (outs DataRC:$vdata), dns> {
let InOperandList = !con((ins AddrRC:$vaddr0, SReg_256_XNULL:$srsrc, DMask:$dmask,
Expand Down Expand Up @@ -508,7 +508,7 @@ class VIMAGE_NoSampler_gfx12<mimgopc op, string opcode,
}

class VSAMPLE_Sampler_gfx12<mimgopc op, string opcode, RegisterOperand DataRC,
int num_addrs, RegisterClass Addr3RC = VGPR_32,
int num_addrs, RegisterOperand Addr3RC = VGPROp_32,
string dns="">
: VSAMPLE_gfx12<op.GFX12, (outs DataRC:$vdata), num_addrs, dns, Addr3RC> {
let InOperandList = !con(AddrIns,
Expand All @@ -525,7 +525,7 @@ class VSAMPLE_Sampler_gfx12<mimgopc op, string opcode, RegisterOperand DataRC,
}

class VSAMPLE_Sampler_nortn_gfx12<mimgopc op, string opcode,
int num_addrs, RegisterClass Addr3RC = VGPR_32,
int num_addrs, RegisterOperand Addr3RC = VGPROp_32,
string dns="">
: VSAMPLE_gfx12<op.GFX12, (outs), num_addrs, dns, Addr3RC> {
let InOperandList = !con(AddrIns,
Expand All @@ -550,16 +550,16 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
let VAddrDwords = 1 in {
let ssamp = 0 in {
if op.HAS_GFX10M then {
def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPROp_32,
!if(enableDisasm, "GFX8", "")>;
if !not(ExtendedImageInst) then
def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32,
def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPROp_32,
!if(enableDisasm, "GFX90A", "")>;
def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32,
def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPROp_32,
!if(enableDisasm, "GFX10", "")>;
}
if op.HAS_GFX11 then {
def _V1_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPR_32,
def _V1_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPROp_32,
!if(enableDisasm, "GFX11", "")>;
}
}
Expand All @@ -576,14 +576,14 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
let VAddrDwords = 2 in {
let ssamp = 0 in {
if op.HAS_GFX10M then {
def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_64>;
def _V2 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPROp_64>;
if !not(ExtendedImageInst) then
def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_64_Align2>;
def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_64>;
def _V2_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPROp_64_Align2>;
def _V2_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPROp_64>;
def _V2_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 2>;
}
if op.HAS_GFX11 then {
def _V2_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_64>;
def _V2_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPROp_64>;
def _V2_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 2>;
}
}
Expand All @@ -600,14 +600,14 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
let VAddrDwords = 3 in {
let ssamp = 0 in {
if op.HAS_GFX10M then {
def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_96>;
def _V3 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPROp_96>;
if !not(ExtendedImageInst) then
def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_96_Align2>;
def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_96>;
def _V3_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPROp_96_Align2>;
def _V3_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPROp_96>;
def _V3_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 3>;
}
if op.HAS_GFX11 then {
def _V3_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_96>;
def _V3_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPROp_96>;
def _V3_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 3>;
}
}
Expand All @@ -624,23 +624,23 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
let VAddrDwords = 4 in {
let ssamp = 0 in {
if op.HAS_GFX10M then {
def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VReg_128>;
def _V4 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPROp_128>;
if !not(ExtendedImageInst) then
def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128_Align2>;
def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>;
def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPROp_128_Align2>;
def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPROp_128>;
def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4,
!if(enableDisasm, "GFX10", "")>;
}
if op.HAS_GFX11 then {
def _V4_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_128>;
def _V4_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPROp_128>;
def _V4_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 4,
!if(enableDisasm, "GFX11", "")>;
}
}
if op.HAS_GFX12 then {
if isVSample then {
let samp = 0 in
def _V4_gfx12 : VSAMPLE_Sampler_gfx12<op, asm, dst_rc, 4, VGPR_32,
def _V4_gfx12 : VSAMPLE_Sampler_gfx12<op, asm, dst_rc, 4, VGPROp_32,
!if(enableDisasm, "GFX12", "")>;
}
else {
Expand Down Expand Up @@ -1128,7 +1128,7 @@ multiclass MIMG_Atomic_Renamed <mimgopc op, string asm, string renamed,
: MIMG_Atomic <op, asm, isCmpSwap, isFP, renamed>;

class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterOperand dst_rc,
RegisterClass src_rc, string dns="">
RegisterOperand src_rc, string dns="">
: MIMG_gfx6789 <op.VI, (outs dst_rc:$vdata), dns> {
let InOperandList = !con((ins src_rc:$vaddr, SReg_256_XNULL:$srsrc, SReg_128_XNULL:$ssamp,
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
Expand All @@ -1139,7 +1139,7 @@ class MIMG_Sampler_Helper <mimgopc op, string asm, RegisterOperand dst_rc,
}

class MIMG_Sampler_gfx90a<mimgopc op, string asm, RegisterOperand dst_rc,
RegisterClass src_rc, string dns="">
RegisterOperand src_rc, string dns="">
: MIMG_gfx90a<op.GFX10M, (outs dst_rc:$vdata), dns> {
let InOperandList = !con((ins src_rc:$vaddr, SReg_256_XNULL:$srsrc, SReg_128_XNULL:$ssamp,
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
Expand All @@ -1164,7 +1164,7 @@ class MIMG_Sampler_Asm_gfx10p<string opcode, string AsmPrefix, bit HasD16> {
}

class MIMG_Sampler_gfx10<mimgopc op, string opcode,
RegisterOperand DataRC, RegisterClass AddrRC,
RegisterOperand DataRC, RegisterOperand AddrRC,
string dns="">
: MIMG_gfx10<op.GFX10M, (outs DataRC:$vdata), dns> {
let InOperandList = MIMG_Sampler_OpList_gfx10p<(ins AddrRC:$vaddr0), BaseOpcode.HasD16>.ret;
Expand All @@ -1180,7 +1180,7 @@ class MIMG_Sampler_nsa_gfx10<mimgopc op, string opcode,
}

class MIMG_Sampler_nortn_gfx10<mimgopc op, string opcode,
RegisterClass AddrRC,
RegisterOperand AddrRC,
string dns="">
: MIMG_gfx10<op.GFX10M, (outs), dns> {
let InOperandList = MIMG_Sampler_OpList_gfx10p<(ins AddrRC:$vaddr0), BaseOpcode.HasD16>.ret;
Expand All @@ -1200,7 +1200,7 @@ class MIMG_Sampler_nortn_nsa_gfx10<mimgopc op, string opcode,
}

class MIMG_Sampler_gfx11<mimgopc op, string opcode,
RegisterOperand DataRC, RegisterClass AddrRC,
RegisterOperand DataRC, RegisterOperand AddrRC,
string dns="">
: MIMG_gfx11<op.GFX11, (outs DataRC:$vdata), dns> {
let InOperandList = MIMG_Sampler_OpList_gfx10p<(ins AddrRC:$vaddr0), BaseOpcode.HasD16>.ret;
Expand All @@ -1209,15 +1209,15 @@ class MIMG_Sampler_gfx11<mimgopc op, string opcode,

class MIMG_Sampler_nsa_gfx11<mimgopc op, string opcode,
RegisterOperand DataRC, int num_addrs,
RegisterClass LastVAddrSize, string dns="">
RegisterOperand LastVAddrSize, string dns="">
: MIMG_nsa_gfx11<op.GFX11, (outs DataRC:$vdata), num_addrs, dns, [],
LastVAddrSize> {
let InOperandList = MIMG_Sampler_OpList_gfx10p<AddrIns, BaseOpcode.HasD16>.ret;
let AsmString = MIMG_Sampler_Asm_gfx10p<opcode, " $vdata, "#AddrAsm, BaseOpcode.HasD16>.ret;
}

class MIMG_Sampler_nortn_gfx11<mimgopc op, string opcode,
RegisterClass AddrRC,
RegisterOperand AddrRC,
string dns="">
: MIMG_gfx11<op.GFX11, (outs), dns> {
let InOperandList = MIMG_Sampler_OpList_gfx10p<(ins AddrRC:$vaddr0), BaseOpcode.HasD16>.ret;
Expand All @@ -1227,7 +1227,7 @@ class MIMG_Sampler_nortn_gfx11<mimgopc op, string opcode,

class MIMG_Sampler_nortn_nsa_gfx11<mimgopc op, string opcode,
int num_addrs,
RegisterClass LastVAddrSize, string dns="">
RegisterOperand LastVAddrSize, string dns="">
: MIMG_nsa_gfx11<op.GFX11, (outs), num_addrs, dns, [], LastVAddrSize> {
let InOperandList = MIMG_Sampler_OpList_gfx10p<AddrIns, BaseOpcode.HasD16>.ret;
let AsmString = MIMG_Sampler_Asm_gfx10p<opcode, "off, "#AddrAsm, BaseOpcode.HasD16>.ret;
Expand All @@ -1237,20 +1237,20 @@ class MIMG_Sampler_nortn_nsa_gfx11<mimgopc op, string opcode,
class MIMGAddrSize<int dw, bit enable_disasm, int AddrDW = dw> {
int NumWords = dw;

RegisterClass RegClass = !if(!le(AddrDW, 0), ?,
!if(!eq(AddrDW, 1), VGPR_32,
!if(!eq(AddrDW, 2), VReg_64,
!if(!eq(AddrDW, 3), VReg_96,
!if(!eq(AddrDW, 4), VReg_128,
!if(!eq(AddrDW, 5), VReg_160,
!if(!eq(AddrDW, 6), VReg_192,
!if(!eq(AddrDW, 7), VReg_224,
!if(!eq(AddrDW, 8), VReg_256,
!if(!eq(AddrDW, 9), VReg_288,
!if(!eq(AddrDW, 10), VReg_320,
!if(!eq(AddrDW, 11), VReg_352,
!if(!eq(AddrDW, 12), VReg_384,
!if(!le(AddrDW, 16), VReg_512, ?))))))))))))));
RegisterOperand RegClass = !if(!le(AddrDW, 0), ?,
Copy link
Collaborator

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

nit: !cond() would look better.

!if(!eq(AddrDW, 1), VGPROp_32,
!if(!eq(AddrDW, 2), VGPROp_64,
!if(!eq(AddrDW, 3), VGPROp_96,
!if(!eq(AddrDW, 4), VGPROp_128,
!if(!eq(AddrDW, 5), VGPROp_160,
!if(!eq(AddrDW, 6), VGPROp_192,
!if(!eq(AddrDW, 7), VGPROp_224,
!if(!eq(AddrDW, 8), VGPROp_256,
!if(!eq(AddrDW, 9), VGPROp_288,
!if(!eq(AddrDW, 10), VGPROp_320,
!if(!eq(AddrDW, 11), VGPROp_352,
!if(!eq(AddrDW, 12), VGPROp_384,
!if(!le(AddrDW, 16), VGPROp_512, ?))))))))))))));

// Whether the instruction variant with this vaddr size should be enabled for
// the auto-generated disassembler.
Expand Down Expand Up @@ -1514,8 +1514,10 @@ multiclass MIMG_Gather_WQM <mimgopc op, AMDGPUSampleVariant sample>

class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual, bit isBVH8> {
int num_addrs = !if(isBVH8, 11, !if(Is64, !if(IsA16, 9, 12), !if(IsA16, 8, 11)));
RegisterClass RegClass = MIMGAddrSize<num_addrs, 0>.RegClass;
int VAddrDwords = !srl(RegClass.Size, 5);
RegisterOperand RegClass = MIMGAddrSize<num_addrs, 0>.RegClass;

defvar Size = !cast<SIRegisterClass>(RegClass.RegClass).Size;
int VAddrDwords = !srl(Size, 5);

int GFX11PlusNSAAddrs = !if(IsA16, 4, 5);
RegisterClass node_ptr_type = !if(Is64, VReg_64, VGPR_32);
Expand All @@ -1526,7 +1528,7 @@ class MIMG_IntersectRay_Helper<bit Is64, bit IsA16, bit isDual, bit isBVH8> {
true : [node_ptr_type, VGPR_32, VReg_96, VReg_96, VReg_96]);
}

class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC>
class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterOperand AddrRC>
: MIMG_gfx10<op.GFX10M, (outs VReg_128:$vdata), "GFX10"> {
let InOperandList = (ins AddrRC:$vaddr0, SReg_128_XNULL:$srsrc, A16:$a16);
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";
Expand All @@ -1540,7 +1542,7 @@ class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs>
let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc$a16";
}

class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterClass AddrRC>
class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterOperand AddrRC>
: MIMG_gfx11<op.GFX11, (outs VReg_128:$vdata), "GFX11"> {
let InOperandList = (ins AddrRC:$vaddr0, SReg_128_XNULL:$srsrc, A16:$a16);
let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";
Expand Down
20 changes: 19 additions & 1 deletion llvm/lib/Target/AMDGPU/SIInstrInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -2596,24 +2596,42 @@ class getAlign2RegOp<RegisterOperand RC> {
RegisterOperand ret =
!cond(!eq(RC, VGPROp_16) : VGPROp_16,
!eq(RC, VGPROp_32) : VGPROp_32,

!eq(RC, VGPROp_64) : VGPROp_64_Align2,
!eq(RC, VGPROp_64_Align1) : VGPROp_64_Align2,
!eq(RC, VGPROp_64_Align2) : VGPROp_64_Align2,

!eq(RC, VGPROp_96) : VGPROp_96_Align2,
!eq(RC, VGPROp_96_Align1) : VGPROp_96_Align2,
!eq(RC, VGPROp_96_Align2) : VGPROp_96_Align2,

!eq(RC, VGPROp_128) : VGPROp_128_Align2,
!eq(RC, VGPROp_128_Align1) : VGPROp_128_Align2,
!eq(RC, VGPROp_128_Align2) : VGPROp_128_Align2,

!eq(RC, VGPROp_160) : VGPROp_160_Align2,
!eq(RC, VGPROp_160_Align1) : VGPROp_160_Align2,
!eq(RC, VGPROp_160_Align2) : VGPROp_160_Align2,

!eq(RC, VGPROp_1024) : VGPROp_1024_Align2,
!eq(RC, VGPROp_1024_Align1) : VGPROp_1024_Align2,
!eq(RC, VGPROp_1024_Align2) : VGPROp_1024_Align2,

!eq(RC, AVLdSt_32) : AVLdSt_32,
!eq(RC, AVLdSt_64_Align1) : AVLdSt_64_Align2,
!eq(RC, AVLdSt_64) : AVLdSt_64_Align2,

!eq(RC, AVLdSt_96) : AVLdSt_96_Align2,
!eq(RC, AVLdSt_96_Align1) : AVLdSt_96_Align1,
!eq(RC, AVLdSt_96_Align1) : AVLdSt_96_Align2,

!eq(RC, AVLdSt_128) : AVLdSt_128_Align2,
!eq(RC, AVLdSt_128_Align1) : AVLdSt_128_Align2,
!eq(RC, AVLdSt_128_Align2) : AVLdSt_128_Align2,

!eq(RC, AVLdSt_160) : AVLdSt_160_Align2,
!eq(RC, AVLdSt_160_Align1) : AVLdSt_160_Align2);
!eq(RC, AVLdSt_160_Align1) : AVLdSt_160_Align2,
!eq(RC, AVLdSt_160_Align2) : AVLdSt_160_Align2);
}

class getEquivalentAGPROperand<RegisterOperand RC> {
Expand Down
2 changes: 1 addition & 1 deletion llvm/lib/Target/AMDGPU/SIRegisterInfo.td
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1327,7 +1327,7 @@ def VGPROp_16 : VGPROp<VGPR_16> {
}
def VGPROp_32 : VGPROp<VGPR_32>;

foreach size = ["64", "96", "128", "160", "192", "224", "256", "288", "512", "1024"] in {
foreach size = ["64", "96", "128", "160", "192", "224", "256", "288", "320", "352", "384", "512", "1024"] in {
def VGPROp_#size : VGPROp<!cast<RegisterClass>("VReg_"#size)>;
}

Expand Down