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AMDGPU: Stop checking allocatable in adjustAllocatableRegClass #158105

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Merged
merged 1 commit into from
Sep 11, 2025
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AMDGPU: Stop checking allocatable in adjustAllocatableRegClass #158105

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14 changes: 6 additions & 8 deletions llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5975,12 +5975,10 @@ SIInstrInfo::getWholeWaveFunctionSetup(MachineFunction &MF) const {

static const TargetRegisterClass *
adjustAllocatableRegClass(const GCNSubtarget &ST, const SIRegisterInfo &RI,
const MCInstrDesc &TID, unsigned RCID,
bool IsAllocatable) {
if ((IsAllocatable || !ST.hasGFX90AInsts()) &&
(((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::Spill)) ||
(TID.TSFlags & SIInstrFlags::MIMG))) {
const MCInstrDesc &TID, unsigned RCID) {
if (!ST.hasGFX90AInsts() && (((TID.mayLoad() || TID.mayStore()) &&
!(TID.TSFlags & SIInstrFlags::Spill)) ||
(TID.TSFlags & SIInstrFlags::MIMG))) {
switch (RCID) {
case AMDGPU::AV_32RegClassID:
RCID = AMDGPU::VGPR_32RegClassID;
Expand Down Expand Up @@ -6020,7 +6018,7 @@ const TargetRegisterClass *SIInstrInfo::getRegClass(const MCInstrDesc &TID,
return RI.getRegClass(RegClass);
}

return adjustAllocatableRegClass(ST, RI, TID, RegClass, false);
return adjustAllocatableRegClass(ST, RI, TID, RegClass);
}

const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
Expand All @@ -6039,7 +6037,7 @@ const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
}

unsigned RCID = Desc.operands()[OpNo].RegClass;
return adjustAllocatableRegClass(ST, RI, Desc, RCID, true);
return adjustAllocatableRegClass(ST, RI, Desc, RCID);
}

void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
Expand Down
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