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[PowerPC] Implement VSX Vector Integer Arithmetic Instructions #158363

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Sep 24, 2025
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[PowerPC] Implement VSX Vector Integer Arithmetic Instructions #158363

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9783e14
[PowerPC] Implement VSX Vector Integer Arithmetic Instructions
lei137 Sep 10, 2025
d527b8a
update to add opcode to class var since this class is needed for impl…
lei137 Sep 10, 2025
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41 changes: 41 additions & 0 deletions llvm/lib/Target/PowerPC/PPCInstrFuture.td
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Original file line number Diff line number Diff line change
Expand Up @@ -183,6 +183,25 @@ class XX3Form_XTAB6_P1<bits<5> xo, dag OOL, dag IOL, string asmstr,
let Inst{31} = XT{5};
}

class XX3Form_XTAB6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
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just curious, is there any rule for the name of the instruction format class ?

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Yes, it's documented in llvm/lib/Target/PowerPC/PPCInstrP10.td

list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, NoItinerary> {

bits<6> XT;
bits<6> XA;
bits<6> XB;

let Pattern = pattern;

let Inst{6...10} = XT{4...0};
let Inst{11...15} = XA{4...0};
let Inst{16...20} = XB{4...0};
let Inst{21...28} = xo;
let Inst{29} = XA{5};
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double confirm : the MSB of XA,XT,XB is {5}, LSB is {0} ?

let Inst{30} = XB{5};
let Inst{31} = XT{5};
}

//-------------------------- Instruction definitions -------------------------//
// Predicate combinations available:
// [IsISAFuture]
Expand Down Expand Up @@ -273,6 +292,28 @@ let Predicates = [HasVSX, IsISAFuture] in {
def XXGFMUL128 : XX3Form_XTAB6_P1<26, (outs vsrc:$XT),
(ins vsrc:$XA, vsrc:$XB, u1imm:$P),
"xxgfmul128 $XT, $XA, $XB, $P", []>;

// VSX Vector Integer Arithmetic Instructions
def XVADDUWM : XX3Form_XTAB6<60, 131, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvadduwm $XT, $XA, $XB", []>;
def XVADDUHM : XX3Form_XTAB6<60, 139, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvadduhm $XT, $XA, $XB", []>;
def XVSUBUWM: XX3Form_XTAB6<60, 147, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvsubuwm $XT, $XA, $XB", []>;
def XVSUBUHM: XX3Form_XTAB6<60, 155, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvsubuhm $XT, $XA, $XB", []>;
def XVMULUWM: XX3Form_XTAB6<60, 163, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvmuluwm $XT, $XA, $XB", []>;
def XVMULUHM: XX3Form_XTAB6<60, 171, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvmuluhm $XT, $XA, $XB", []>;
def XVMULHSW: XX3Form_XTAB6<60, 179, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvmulhsw $XT, $XA, $XB", []>;
def XVMULHSH: XX3Form_XTAB6<60, 187, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvmulhsh $XT, $XA, $XB", []>;
def XVMULHUW: XX3Form_XTAB6<60, 114, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvmulhuw $XT, $XA, $XB", []>;
def XVMULHUH: XX3Form_XTAB6<60, 122, (outs vsrc:$XT), (ins vsrc:$XA, vsrc:$XB),
"xvmulhuh $XT, $XA, $XB", []>;
}

//---------------------------- Anonymous Patterns ----------------------------//
Expand Down
30 changes: 30 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
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Expand Up @@ -243,3 +243,33 @@

#CHECK: xxgfmul128gcm 7, 5, 4
0xf0,0xe5,0x26,0xd0

#CHECK: xvadduwm 4, 5, 7
0xf0,0x85,0x3c,0x18

#CHECK: xvadduhm 4, 5, 7
0xf0,0x85,0x3c,0x58

#CHECK: xvsubuwm 4, 5, 7
0xf0,0x85,0x3c,0x98

#CHECK: xvsubuhm 4, 5, 7
0xf0,0x85,0x3c,0xd8

#CHECK: xvmuluwm 4, 5, 7
0xf0,0x85,0x3d,0x18

#CHECK: xvmuluhm 4, 5, 7
0xf0,0x85,0x3d,0x58

#CHECK: xvmulhsw 4, 5, 7
0xf0,0x85,0x3d,0x98

#CHECK: xvmulhsh 4, 5, 7
0xf0,0x85,0x3d,0xd8

#CHECK: xvmulhuw 4, 5, 7
0xf0,0x85,0x3b,0x90

#CHECK: xvmulhuh 4, 5, 7
0xf0,0x85,0x3b,0xd0
30 changes: 30 additions & 0 deletions llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
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Expand Up @@ -237,3 +237,33 @@

#CHECK: xxgfmul128gcm 7, 5, 4
0xd0,0x26,0xe5,0xf0

#CHECK: xvadduwm 4, 5, 7
0x18,0x3c,0x85,0xf0

#CHECK: xvadduhm 4, 5, 7
0x58,0x3c,0x85,0xf0

#CHECK: xvsubuwm 4, 5, 7
0x98,0x3c,0x85,0xf0

#CHECK: xvsubuhm 4, 5, 7
0xd8,0x3c,0x85,0xf0

#CHECK: xvmuluwm 4, 5, 7
0x18,0x3d,0x85,0xf0

#CHECK: xvmuluhm 4, 5, 7
0x58,0x3d,0x85,0xf0

#CHECK: xvmulhsw 4, 5, 7
0x98,0x3d,0x85,0xf0

#CHECK: xvmulhsh 4, 5, 7
0xd8,0x3d,0x85,0xf0

#CHECK: xvmulhuw 4, 5, 7
0x90,0x3b,0x85,0xf0

#CHECK: xvmulhuh 4, 5, 7
0xd0,0x3b,0x85,0xf0
40 changes: 40 additions & 0 deletions llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
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Expand Up @@ -346,3 +346,43 @@
xxgfmul128gcm 7, 5, 4
#CHECK-BE: xxgfmul128gcm 7, 5, 4 # encoding: [0xf0,0xe5,0x26,0xd0]
#CHECK-LE: xxgfmul128gcm 7, 5, 4 # encoding: [0xd0,0x26,0xe5,0xf0]

xvadduwm 4, 5, 7
#CHECK-BE: xvadduwm 4, 5, 7 # encoding: [0xf0,0x85,0x3c,0x18]
#CHECK-LE: xvadduwm 4, 5, 7 # encoding: [0x18,0x3c,0x85,0xf0]

xvadduhm 4, 5, 7
#CHECK-BE: xvadduhm 4, 5, 7 # encoding: [0xf0,0x85,0x3c,0x58]
#CHECK-LE: xvadduhm 4, 5, 7 # encoding: [0x58,0x3c,0x85,0xf0]

xvsubuwm 4, 5, 7
#CHECK-BE: xvsubuwm 4, 5, 7 # encoding: [0xf0,0x85,0x3c,0x98]
#CHECK-LE: xvsubuwm 4, 5, 7 # encoding: [0x98,0x3c,0x85,0xf0]

xvsubuhm 4, 5, 7
#CHECK-BE: xvsubuhm 4, 5, 7 # encoding: [0xf0,0x85,0x3c,0xd8]
#CHECK-LE: xvsubuhm 4, 5, 7 # encoding: [0xd8,0x3c,0x85,0xf0]

xvmuluwm 4, 5, 7
#CHECK-BE: xvmuluwm 4, 5, 7 # encoding: [0xf0,0x85,0x3d,0x18]
#CHECK-LE: xvmuluwm 4, 5, 7 # encoding: [0x18,0x3d,0x85,0xf0]

xvmuluhm 4, 5, 7
#CHECK-BE: xvmuluhm 4, 5, 7 # encoding: [0xf0,0x85,0x3d,0x58]
#CHECK-LE: xvmuluhm 4, 5, 7 # encoding: [0x58,0x3d,0x85,0xf0]

xvmulhsw 4, 5, 7
#CHECK-BE: xvmulhsw 4, 5, 7 # encoding: [0xf0,0x85,0x3d,0x98]
#CHECK-LE: xvmulhsw 4, 5, 7 # encoding: [0x98,0x3d,0x85,0xf0]

xvmulhsh 4, 5, 7
#CHECK-BE: xvmulhsh 4, 5, 7 # encoding: [0xf0,0x85,0x3d,0xd8]
#CHECK-LE: xvmulhsh 4, 5, 7 # encoding: [0xd8,0x3d,0x85,0xf0]

xvmulhuw 4, 5, 7
#CHECK-BE: xvmulhuw 4, 5, 7 # encoding: [0xf0,0x85,0x3b,0x90]
#CHECK-LE: xvmulhuw 4, 5, 7 # encoding: [0x90,0x3b,0x85,0xf0]

xvmulhuh 4, 5, 7
#CHECK-BE: xvmulhuh 4, 5, 7 # encoding: [0xf0,0x85,0x3b,0xd0]
#CHECK-LE: xvmulhuh 4, 5, 7 # encoding: [0xd0,0x3b,0x85,0xf0]