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[LegalizeTypes][X86] Use getShiftAmountConstant in ExpandIntRes_SIGN_EXTEND. #158388

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Merged
merged 2 commits into from
Sep 13, 2025
Merged

[LegalizeTypes][X86] Use getShiftAmountConstant in ExpandIntRes_SIGN_EXTEND. #158388

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2e93762
[LegalizeTypes][X86] Use getShiftAmountConstant in ExpandIntRes_SIGN_…
topperc Sep 13, 2025
7aaa08b
fixup! remove accidental changes.
topperc Sep 13, 2025
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9 changes: 4 additions & 5 deletions llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5088,9 +5088,8 @@ void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
Lo = DAG.getNode(ISD::SIGN_EXTEND, dl, NVT, N->getOperand(0));
// The high part is obtained by SRA'ing all but one of the bits of low part.
unsigned LoSize = NVT.getSizeInBits();
Hi = DAG.getNode(
ISD::SRA, dl, NVT, Lo,
DAG.getConstant(LoSize - 1, dl, TLI.getPointerTy(DAG.getDataLayout())));
Hi = DAG.getNode(ISD::SRA, dl, NVT, Lo,
DAG.getShiftAmountConstant(LoSize - 1, NVT, dl));
} else {
// For example, extension of an i48 to an i64. The operand type necessarily
// promotes to the result type, so will end up being expanded too.
Expand Down Expand Up @@ -5123,8 +5122,8 @@ ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
// The high part gets the sign extension from the lo-part. This handles
// things like sextinreg V:i64 from i8.
Hi = DAG.getNode(ISD::SRA, dl, Hi.getValueType(), Lo,
DAG.getConstant(Hi.getValueSizeInBits() - 1, dl,
TLI.getPointerTy(DAG.getDataLayout())));
DAG.getShiftAmountConstant(Hi.getValueSizeInBits() - 1,
Hi.getValueType(), dl));
} else {
// For example, extension of an i48 to an i64. Leave the low part alone,
// sext_inreg the high part.
Expand Down
8 changes: 6 additions & 2 deletions llvm/lib/Target/X86/X86ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -48396,13 +48396,17 @@ static SDValue checkSignTestSetCCCombine(SDValue Cmp, X86::CondCode &CC,
MVT SrcVT = Src.getSimpleValueType();
APInt BitMask = APInt::getSignMask(SrcVT.getScalarSizeInBits());

// If Src came from a SHL (probably from an expanded SIGN_EXTEND_INREG), then
// peek through and adjust the TEST bit.
// If Src came from a SIGN_EXTEND_INREG or SHL (probably from an expanded
// SIGN_EXTEND_INREG), then peek through and adjust the TEST bit.
if (Src.getOpcode() == ISD::SHL) {
if (std::optional<unsigned> ShiftAmt = DAG.getValidShiftAmount(Src)) {
Src = Src.getOperand(0);
BitMask.lshrInPlace(*ShiftAmt);
}
} else if (Src.getOpcode() == ISD::SIGN_EXTEND_INREG) {
EVT ExtVT = cast<VTSDNode>(Src.getOperand(1))->getVT();
Src = Src.getOperand(0);
BitMask.lshrInPlace(BitMask.getBitWidth() - ExtVT.getScalarSizeInBits());
}

SDValue Mask = DAG.getNode(ISD::AND, DL, SrcVT, Src,
Expand Down