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[AMDGPU][MC] Keep MCOperands unencoded. #158685

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Merged
merged 1 commit into from
Sep 16, 2025
Merged

[AMDGPU][MC] Keep MCOperands unencoded. #158685

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81 changes: 12 additions & 69 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2436,17 +2436,8 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
case AMDGPU::OPERAND_REG_IMM_V2FP32:
case AMDGPU::OPERAND_REG_IMM_V2INT32:
case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
if (isSafeTruncation(Val, 32) &&
AMDGPU::isInlinableLiteral32(static_cast<int32_t>(Val),
AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Val));
return;
}
[[fallthrough]];

case AMDGPU::OPERAND_REG_IMM_NOINLINE_V2FP16:

Inst.addOperand(MCOperand::createImm(Lo_32(Val)));
Inst.addOperand(MCOperand::createImm(Val));
return;

case AMDGPU::OPERAND_REG_IMM_INT64:
Expand Down Expand Up @@ -2494,77 +2485,27 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo

case AMDGPU::OPERAND_REG_IMM_INT16:
case AMDGPU::OPERAND_REG_INLINE_C_INT16:
if (isSafeTruncation(Val, 16) &&
AMDGPU::isInlinableIntLiteral(static_cast<int16_t>(Val))) {
Inst.addOperand(MCOperand::createImm(Lo_32(Val)));
return;
}

Inst.addOperand(MCOperand::createImm(Val & 0xffff));
return;

case AMDGPU::OPERAND_REG_INLINE_C_FP16:
case AMDGPU::OPERAND_REG_IMM_FP16:
if (isSafeTruncation(Val, 16) &&
AMDGPU::isInlinableLiteralFP16(static_cast<int16_t>(Val),
AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Val));
return;
}

Inst.addOperand(MCOperand::createImm(Val & 0xffff));
return;

case AMDGPU::OPERAND_REG_IMM_BF16:
case AMDGPU::OPERAND_REG_INLINE_C_BF16:
if (isSafeTruncation(Val, 16) &&
AMDGPU::isInlinableLiteralBF16(static_cast<int16_t>(Val),
AsmParser->hasInv2PiInlineImm())) {
Inst.addOperand(MCOperand::createImm(Val));
return;
}

Inst.addOperand(MCOperand::createImm(Val & 0xffff));
return;

case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: {
assert(isSafeTruncation(Val, 16));
assert(AMDGPU::isInlinableIntLiteral(static_cast<int16_t>(Val)));
Inst.addOperand(MCOperand::createImm(Val));
return;
}
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: {
assert(isSafeTruncation(Val, 16));
assert(AMDGPU::isInlinableLiteralFP16(static_cast<int16_t>(Val),
AsmParser->hasInv2PiInlineImm()));

Inst.addOperand(MCOperand::createImm(Val));
return;
}

case AMDGPU::OPERAND_REG_INLINE_C_V2BF16: {
assert(isSafeTruncation(Val, 16));
assert(AMDGPU::isInlinableLiteralBF16(static_cast<int16_t>(Val),
AsmParser->hasInv2PiInlineImm()));

Inst.addOperand(MCOperand::createImm(Val));
return;
}

case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
case AMDGPU::OPERAND_REG_INLINE_C_V2BF16:
case AMDGPU::OPERAND_KIMM32:
Inst.addOperand(MCOperand::createImm(Literal.getLoBits(32).getZExtValue()));
return;
case AMDGPU::OPERAND_KIMM16:
Inst.addOperand(MCOperand::createImm(Literal.getLoBits(16).getZExtValue()));
Inst.addOperand(MCOperand::createImm(Val));
return;

case AMDGPU::OPERAND_KIMM64:
if ((isInt<32>(Val) || isUInt<32>(Val)) && !getModifiers().Lit64)
Val <<= 32;

Inst.addOperand(MCOperand::createImm(Val));
return;

default:
llvm_unreachable("invalid operand size");
llvm_unreachable("invalid operand type");
}
}

Expand Down Expand Up @@ -4830,7 +4771,7 @@ bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst,

unsigned NumExprs = 0;
unsigned NumLiterals = 0;
uint64_t LiteralValue;
int64_t LiteralValue;

for (int OpIdx : OpIndices) {
if (OpIdx == -1) break;
Expand All @@ -4839,7 +4780,9 @@ bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst,
// Exclude special imm operands (like that used by s_set_gpr_idx_on)
if (AMDGPU::isSISrcOperand(Desc, OpIdx)) {
if (MO.isImm() && !isInlineConstant(Inst, OpIdx)) {
uint64_t Value = static_cast<uint64_t>(MO.getImm());
auto OpType = static_cast<AMDGPU::OperandType>(
Desc.operands()[OpIdx].OperandType);
int64_t Value = encode32BitLiteral(MO.getImm(), OpType);
if (NumLiterals == 0 || LiteralValue != Value) {
LiteralValue = Value;
++NumLiterals;
Expand Down
5 changes: 3 additions & 2 deletions llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -464,8 +464,9 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
assert(STI.hasFeature(AMDGPU::Feature64BitLiterals));
support::endian::write<uint64_t>(CB, Imm, llvm::endianness::little);
} else {
if (Desc.operands()[i].OperandType == AMDGPU::OPERAND_REG_IMM_FP64)
Imm = Hi_32(Imm);
auto OpType =
static_cast<AMDGPU::OperandType>(Desc.operands()[i].OperandType);
Imm = AMDGPU::encode32BitLiteral(Imm, OpType);
support::endian::write<uint32_t>(CB, Imm, llvm::endianness::little);
}

Expand Down
28 changes: 28 additions & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3157,6 +3157,34 @@ bool isValid32BitLiteral(uint64_t Val, bool IsFP64) {
return isUInt<32>(Val) || isInt<32>(Val);
}

int64_t encode32BitLiteral(int64_t Imm, OperandType Type) {
switch (Type) {
default:
break;
case OPERAND_REG_IMM_BF16:
case OPERAND_REG_IMM_FP16:
case OPERAND_REG_INLINE_C_BF16:
case OPERAND_REG_INLINE_C_FP16:
return Imm & 0xffff;
case OPERAND_INLINE_SPLIT_BARRIER_INT32:
case OPERAND_REG_IMM_FP32:
case OPERAND_REG_IMM_INT32:
case OPERAND_REG_IMM_V2BF16:
case OPERAND_REG_IMM_V2FP16:
case OPERAND_REG_IMM_V2FP32:
case OPERAND_REG_IMM_V2INT16:
case OPERAND_REG_IMM_V2INT32:
case OPERAND_REG_INLINE_AC_FP32:
case OPERAND_REG_INLINE_AC_INT32:
case OPERAND_REG_INLINE_C_FP32:
case OPERAND_REG_INLINE_C_INT32:
return Lo_32(Imm);
case OPERAND_REG_IMM_FP64:
return Hi_32(Imm);
}
return Imm;
}

bool isArgPassedInSGPR(const Argument *A) {
const Function *F = A->getParent();

Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1718,6 +1718,9 @@ bool isInlinableLiteralV2F16(uint32_t Literal);
LLVM_READNONE
bool isValid32BitLiteral(uint64_t Val, bool IsFP64);

LLVM_READNONE
int64_t encode32BitLiteral(int64_t Imm, OperandType Type);

bool isArgPassedInSGPR(const Argument *Arg);

bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo);
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/MC/Disassembler/AMDGPU/gfx10-vop3-literal.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@
# GFX10: v_add_nc_i16 v5, v1, 0xcdab ; encoding: [0x05,0x00,0x0d,0xd7,0x01,0xff,0x01,0x00,0xab,0xcd,0xff,0xff]
0x05,0x00,0x0d,0xd7,0x01,0xff,0x01,0x00,0xab,0xcd,0xff,0xff

# GFX10: v_ceil_f16_e64 v255, 0xabcd clamp ; encoding: [0xff,0x80,0xdc,0xd5,0xff,0x00,0x00,0x00,0xcd,0xab,0xff,0xff]
# GFX10: v_ceil_f16_e64 v255, 0xabcd clamp ; encoding: [0xff,0x80,0xdc,0xd5,0xff,0x00,0x00,0x00,0xcd,0xab,0x00,0x00]
0xff,0x80,0xdc,0xd5,0xff,0x00,0x00,0x00,0xcd,0xab,0xff,0xff

# GFX10: v_min_u16 v5, v1, 0xabcd ; encoding: [0x05,0x00,0x0b,0xd7,0x01,0xff,0x01,0x00,0xcd,0xab,0xff,0xff]
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/MC/Disassembler/AMDGPU/gfx8-literal16.txt
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Expand Up @@ -34,17 +34,17 @@
0xff 0x06 0x02 0x3e 0x00 0x01 0x00 0x00

# non-zero unused bits in constant
# VI: v_add_f16_e32 v1, 0x41, v3 ; encoding: [0xff,0x06,0x02,0x3e,0x41,0x00,0x01,0x00]
# VI: v_add_f16_e32 v1, 0x41, v3 ; encoding: [0xff,0x06,0x02,0x3e,0x41,0x00,0x00,0x00]
0xff 0x06 0x02 0x3e 0x41 0x00 0x01 0x00

# VI: v_add_f16_e32 v1, 0x41, v3 ; encoding: [0xff,0x06,0x02,0x3e,0x41,0x00,0x00,0x01]
# VI: v_add_f16_e32 v1, 0x41, v3 ; encoding: [0xff,0x06,0x02,0x3e,0x41,0x00,0x00,0x00]
0xff 0x06 0x02 0x3e 0x41 0x00 0x00 0x01

# FIXME: This should be able to round trip with literal after instruction
# VI: v_add_f16_e32 v1, 0, v3 ; encoding: [0x80,0x06,0x02,0x3e]
0xff 0x06 0x02 0x3e 0x00 0x00 0x00 0x00

# VI: v_add_f16_e32 v1, 0xffcd, v3 ; encoding: [0xff,0x06,0x02,0x3e,0xcd,0xff,0xff,0xff]
# VI: v_add_f16_e32 v1, 0xffcd, v3 ; encoding: [0xff,0x06,0x02,0x3e,0xcd,0xff,0x00,0x00]
0xff 0x06 0x02 0x3e 0xcd 0xff 0xff 0xff

# VI: v_mul_lo_u16_e32 v2, 0xffcd, v2 ; encoding: [0xff,0x04,0x04,0x52,0xcd,0xff,0xff,0xff]
Expand Down