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Resolves instruction selection failure for v64f16 and v32f32 vector types.

Patch by: Fateme Hosseini

Resolves instruction selection failure for v64f16 and v32f32 vector types.

Patch by: Fateme Hosseini
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@fhossein-quic fhossein-quic marked this pull request as ready for review September 15, 2025 22:59
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llvmbot commented Sep 15, 2025

@llvm/pr-subscribers-backend-hexagon

Author: Fateme Hosseini (fhossein-quic)

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Resolves instruction selection failure for v64f16 and v32f32 vector types.

Patch by: Fateme Hosseini


Full diff: https://github.com/llvm/llvm-project/pull/158740.diff

2 Files Affected:

  • (modified) llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp (+4)
  • (added) llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll (+28)
diff --git a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
index f1fa40c1b9036..4af8c6c6c34c2 100644
--- a/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonISelLoweringHVX.cpp
@@ -355,6 +355,8 @@ HexagonTargetLowering::initializeHVXLowering() {
   setCondCodeAction(ISD::SETULE, MVT::v64f16, Expand);
   setCondCodeAction(ISD::SETUGE, MVT::v64f16, Expand);
   setCondCodeAction(ISD::SETULT, MVT::v64f16, Expand);
+  setCondCodeAction(ISD::SETUO,  MVT::v64f16, Expand);
+  setCondCodeAction(ISD::SETO,   MVT::v64f16, Expand);
 
   setCondCodeAction(ISD::SETNE,  MVT::v32f32, Expand);
   setCondCodeAction(ISD::SETLE,  MVT::v32f32, Expand);
@@ -368,6 +370,8 @@ HexagonTargetLowering::initializeHVXLowering() {
   setCondCodeAction(ISD::SETULE, MVT::v32f32, Expand);
   setCondCodeAction(ISD::SETUGE, MVT::v32f32, Expand);
   setCondCodeAction(ISD::SETULT, MVT::v32f32, Expand);
+  setCondCodeAction(ISD::SETUO,  MVT::v32f32, Expand);
+  setCondCodeAction(ISD::SETO,   MVT::v32f32, Expand);
 
   // Boolean vectors.
 
diff --git a/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
new file mode 100644
index 0000000000000..eeee12e86950f
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/inst_setcc_uno_uo.ll
@@ -0,0 +1,28 @@
+;; RUN: llc --mtriple=hexagon -mattr=+hvxv79,+hvx-length128b %s -o - | FileCheck %s
+
+define dso_local void @store_isnan_f32(ptr %a, ptr %isnan_a) local_unnamed_addr {
+entry:
+  %arrayidx = getelementptr inbounds nuw float, ptr %a, i32 0
+  %0 = load <32 x float>, ptr %arrayidx, align 4
+  %.vectorized = fcmp uno <32 x float> %0, zeroinitializer
+  %.LS.instance = zext <32 x i1> %.vectorized to <32 x i32>
+  %arrayidx1 = getelementptr inbounds nuw i32, ptr %isnan_a, i32 0
+  store <32 x i32> %.LS.instance, ptr %arrayidx1, align 4
+  ret void
+}
+;; CHECK: store_isnan_f32
+;; CHECK: vcmp.eq({{v[0-9]+.w}},{{v[0-9]+.w}})
+
+define dso_local void @store_isnan_f16(ptr  %a, ptr %isnan_a) local_unnamed_addr {
+entry:
+  %arrayidx = getelementptr inbounds nuw half, ptr %a, i32 0
+  %0 = load <64 x half>, ptr %arrayidx, align 2
+  %.vectorized = fcmp uno <64 x half> %0, zeroinitializer
+  %conv.LS.instance = zext <64 x i1> %.vectorized to <64 x i16>
+  %arrayidx1 = getelementptr inbounds nuw i16, ptr %isnan_a, i32 0
+  store <64 x i16> %conv.LS.instance, ptr %arrayidx1, align 2
+  ret void
+}
+
+;; CHECK: store_isnan_f16
+;; CHECK: vcmp.eq({{v[0-9]+.h}},{{v[0-9]+.h}})

@fhossein-quic fhossein-quic marked this pull request as draft September 16, 2025 02:04
@fhossein-quic fhossein-quic marked this pull request as ready for review September 16, 2025 15:44
@fhossein-quic
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Hi @SundeepKushwaha, @SergeiYLarin , and @kaushik-quicinc. Could you please take a look at this patch?

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LGTM!

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Looks good. Please merge.

@iajbar iajbar self-requested a review September 16, 2025 17:34
Comment on lines 68 to 74
; CHECK: store_isordered_f16
; CHECK: [[V_ZERO16:v[0-9]+]] = vxor([[V_ZERO16]],[[V_ZERO16]])
; CHECK: [[V_LOAD16:v[0-9]+]] = vmemu(r0+#0)
; CHECK: [[V_ONES16:v[0-9]+]].h = vsplat([[RO16:r[0-9]+]])
; CHECK: {{q[0-9]+}} = vcmp.eq([[V_LOAD16]].h,[[V_LOAD16]].h)
; CHECK: [[V_OUT16:v[0-9]+]] = vmux({{q[0-9]+}},[[V_ONES16]],[[V_ZERO16]])
; CHECK: vmemu(r1+#0) = [[V_OUT16]]
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Thanks for adding more test cases, but none of these examples here are great because the second operand is 0. Can you add testcases where the second operand to fcmp is not 0?

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Thanks for catching this. I've made changes so that the second operand is a var as well. Please let me know if it addresses your comment

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github-actions bot commented Oct 2, 2025

✅ With the latest revision this PR passed the C/C++ code formatter.

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LGTM

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Resolves instruction selection failure for v64f16 and v32f32 vector types.

Is there an issue open for this? If so could you include it in the commit message (and plan to cherry-pick it to the 21.x release)?

@fhossein-quic
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Resolves instruction selection failure for v64f16 and v32f32 vector types.

Is there an issue open for this? If so could you include it in the commit message (and plan to cherry-pick it to the 21.x release)?

No, I am just cherry-picking patches from downstream LLVM to upstream. This patch is already part of the release.

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Resolves instruction selection failure for v64f16 and v32f32 vector types.

Is there an issue open for this? If so could you include it in the commit message (and plan to cherry-pick it to the 21.x release)?

No, I am just cherry-picking patches from downstream LLVM to upstream. This patch is already part of the release.

I'm referring to the public release/21.x which requires that the change land on the public main first before being cherry-picked.

@fhossein-quic
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Resolves instruction selection failure for v64f16 and v32f32 vector types.

Is there an issue open for this? If so could you include it in the commit message (and plan to cherry-pick it to the 21.x release)?

No, I am just cherry-picking patches from downstream LLVM to upstream. This patch is already part of the release.

I'm referring to the public release/21.x which requires that the change land on the public main first before being cherry-picked.

No, there is no upstream issue open for this.

@iajbar iajbar merged commit aea5399 into llvm:main Oct 3, 2025
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github-actions bot commented Oct 3, 2025

@fhossein-quic Congratulations on having your first Pull Request (PR) merged into the LLVM Project!

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/cherry-pick aea5399

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llvmbot commented Oct 3, 2025

Failed to cherry-pick: aea5399

https://github.com/llvm/llvm-project/actions/runs/18231205992

Please manually backport the fix and push it to your github fork. Once this is done, please create a pull request

@dyung dyung moved this from Needs Triage to Needs Backport PR in LLVM Release Status Oct 4, 2025
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