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[X86] Fixes for AMD znver5 enablement #159237

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Merged
merged 2 commits into from
Sep 17, 2025
Merged

[X86] Fixes for AMD znver5 enablement #159237

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e24544b
[X86] Fixes for AMD znver5 enablement
Umesh-k26 Sep 17, 2025
0919fff
Merge branch 'main' into zn5-fixes
Umesh-k26 Sep 17, 2025
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6 changes: 6 additions & 0 deletions compiler-rt/lib/builtins/cpu_model/x86.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1094,6 +1094,12 @@ static void getAvailableFeatures(unsigned ECX, unsigned EDX, unsigned MaxLeaf,
if (HasExtLeaf8 && ((EBX >> 9) & 1))
setFeature(FEATURE_WBNOINVD);

bool HasExtLeaf21 = MaxExtLevel >= 0x80000021 &&
!getX86CpuIDAndInfo(0x80000021, &EAX, &EBX, &ECX, &EDX);
// AMD cpuid bit for prefetchi is different from Intel
if (HasExtLeaf21 && ((EAX >> 20) & 1))
setFeature(FEATURE_PREFETCHI);

bool HasLeaf14 = MaxLevel >= 0x14 &&
!getX86CpuIDAndInfoEx(0x14, 0x0, &EAX, &EBX, &ECX, &EDX);
if (HasLeaf14 && ((EBX >> 4) & 1))
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12 changes: 9 additions & 3 deletions llvm/lib/TargetParser/Host.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1302,16 +1302,17 @@ static const char *getAMDProcessorTypeAndSubtype(unsigned Family,
case 26:
CPU = "znver5";
*Type = X86::AMDFAM1AH;
if (Model <= 0x77) {
if (Model <= 0x4f || (Model >= 0x60 && Model <= 0x77) ||
(Model >= 0xd0 && Model <= 0xd7)) {
// Models 00h-0Fh (Breithorn).
// Models 10h-1Fh (Breithorn-Dense).
// Models 20h-2Fh (Strix 1).
// Models 30h-37h (Strix 2).
// Models 38h-3Fh (Strix 3).
// Models 40h-4Fh (Granite Ridge).
// Models 50h-5Fh (Weisshorn).
// Models 60h-6Fh (Krackan1).
// Models 70h-77h (Sarlak).
// Models D0h-D7h (Annapurna).
CPU = "znver5";
*Subtype = X86::AMDFAM1AH_ZNVER5;
break; // "znver5"
Expand Down Expand Up @@ -2049,6 +2050,11 @@ StringMap<bool> sys::getHostCPUFeatures() {
Features["rdpru"] = HasExtLeaf8 && ((EBX >> 4) & 1);
Features["wbnoinvd"] = HasExtLeaf8 && ((EBX >> 9) & 1);

bool HasExtLeaf21 = MaxExtLevel >= 0x80000021 &&
!getX86CpuIDAndInfo(0x80000021, &EAX, &EBX, &ECX, &EDX);
// AMD cpuid bit for prefetchi is different from Intel
Features["prefetchi"] = HasExtLeaf21 && ((EAX >> 20) & 1);

bool HasLeaf7 =
MaxLevel >= 7 && !getX86CpuIDAndInfoEx(0x7, 0x0, &EAX, &EBX, &ECX, &EDX);

Expand Down Expand Up @@ -2131,7 +2137,7 @@ StringMap<bool> sys::getHostCPUFeatures() {
Features["avxneconvert"] = HasLeaf7Subleaf1 && ((EDX >> 5) & 1) && HasAVXSave;
Features["amx-complex"] = HasLeaf7Subleaf1 && ((EDX >> 8) & 1) && HasAMXSave;
Features["avxvnniint16"] = HasLeaf7Subleaf1 && ((EDX >> 10) & 1) && HasAVXSave;
Features["prefetchi"] = HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["prefetchi"] |= HasLeaf7Subleaf1 && ((EDX >> 14) & 1);
Features["usermsr"] = HasLeaf7Subleaf1 && ((EDX >> 15) & 1);
bool HasAVX10 = HasLeaf7Subleaf1 && ((EDX >> 19) & 1);
bool HasAPXF = HasLeaf7Subleaf1 && ((EDX >> 21) & 1);
Expand Down