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Merged
merged 3 commits into from
Sep 19, 2025
Merged

[RISC-V] Add P-ext MC Support for Remaining Pair Operations #159247

merged 3 commits into from
Sep 19, 2025

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realqhc
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@realqhc realqhc commented Sep 17, 2025 •
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This patch implements pages 21-24 from jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf

Documentation:
jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf
jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf

@realqhc
[RISC-V] Add P-ext MC Support for Remaining Pair Operations
69300e7 
This patch implements pages 21-24 from jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf

Documentation:
jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf
jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf
@realqhc realqhc requested a review from topperc September 17, 2025 05:53
@llvmbot
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llvmbot commented Sep 17, 2025

@llvm/pr-subscribers-backend-risc-v

Author: Qihan Cai (realqhc)

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This patch implements pages 21-24 from jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf

Documentation:
jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf
jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf

Patch is 26.14 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/159247.diff

3 Files Affected:

  • (modified) llvm/lib/Target/RISCV/RISCVInstrInfoP.td (+258)
  • (modified) llvm/test/MC/RISCV/invalid-instruction-spellcheck.s (+2-2)
  • (modified) llvm/test/MC/RISCV/rv32p-valid.s (+339)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
index 6840dacaea54a..72dd82871985a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td
@@ -132,6 +132,37 @@ class RVPNarrowingBase<bits<3> f, bit r, bits<4> funct4, dag outs, dag ins,
   let Inst{6-0}   = OPC_OP_IMM_32.Value;
 }
 
+// Common base for pair ops (non-widening nor narrowing)
+class RVPPairBase<bits<3> f, bit r, bit direction, dag outs, dag ins,
+                  string opcodestr, string argstr>
+  : RVInst<outs, ins, opcodestr, argstr, [], InstFormatOther> {
+  bits<5> rs1;
+  bits<5> rd;
+
+  let Inst{30-28} = f;
+  let Inst{27}    = r;
+  let Inst{19-16} = rs1{4-1};
+  let Inst{15}    = direction;
+  let Inst{14-12} = 0b110;
+  let Inst{11-8}  = rd{4-1};
+  let Inst{7}     = 0b0;
+  let Inst{6-0}   = OPC_OP_IMM_32.Value;
+}
+
+// Common base for pair binary ops
+class RVPPairBinaryBase_rr<bits<3> f, bit r, bits<2> w, bit pack, bit direction,
+                           string opcodestr>
+    : RVPPairBase<f, r, direction, (outs GPRPairRV32:$rd),
+                  (ins GPRPairRV32:$rs1, GPRPairRV32:$rs2), opcodestr,
+                  "$rd, $rs1, $rs2"> {
+  bits<5> rs2;
+
+  let Inst{31}    = 0b1;
+  let Inst{26-25} = w;
+  let Inst{24-21} = rs2{4-1};
+  let Inst{20}    = pack;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class RVPShift_ri<bits<3> f, bits<3> funct3, string opcodestr, Operand ImmType>
     : RVInstIBase<funct3, OPC_OP_IMM_32, (outs GPR:$rd),
@@ -249,6 +280,39 @@ class RVPNarrowingShiftB_ri<bits<3> f, string opcodestr>
   let Inst{23-20} = shamt;
 }
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPPairShift_ri<bits<3> f, string opcodestr, Operand ImmType, 
+                      bit direction>
+    : RVPPairBase<f, 0b0, direction, (outs GPRPairRV32:$rd),
+                       (ins GPRPairRV32:$rs1, ImmType:$shamt), opcodestr,
+                       "$rd, $rs1, $shamt"> {
+  let Inst{31}    = 0b0;
+}
+
+class RVPPairShiftW_ri<bits<3> f, string opcodestr, bit direction = 0b0>
+    : RVPPairShift_ri<f, opcodestr, uimm5, direction> {
+  bits<5> shamt;
+
+  let Inst{26-25} = 0b01;
+  let Inst{24-20} = shamt;
+}
+
+class RVPPairShiftH_ri<bits<3> f, string opcodestr, bit direction = 0b0>
+    : RVPPairShift_ri<f, opcodestr, uimm4, direction> {
+  bits<4> shamt;
+
+  let Inst{26-24} = 0b001;
+  let Inst{23-20} = shamt;
+}
+
+class RVPPairShiftB_ri<bits<3> f, string opcodestr, bit direction = 0b0>
+    : RVPPairShift_ri<f, opcodestr, uimm3, direction> {
+  bits<3> shamt;
+
+  let Inst{26-23} = 0b0001;
+  let Inst{22-20} = shamt;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class RVPNarrowingShift_rr<bits<3> f, bits<2> w, string opcodestr>
     : RVPNarrowingBase<f, 0b1, 0b1100, (outs GPR:$rd),
@@ -268,6 +332,18 @@ class RVPWideningShift_rr<bits<3> f, bits<2> w, string opcodestr>
   let Inst{27} = 0b1;
 }
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPPairShift_rr<bits<3> f, bits<2> w, string opcodestr,
+                      bit direction = 0b0>
+    : RVPPairBase<f, 0b1, direction, (outs GPRPairRV32:$rd),
+                  (ins GPRPairRV32:$rs1, GPR:$rs2), opcodestr,
+                  "$rd, $rs1, $rs2"> {
+  bits<5> rs2;
+
+  let Inst{26-25} = w;
+  let Inst{24-20} = rs2;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class RVPUnary_ri<bits<2> w, bits<5> uf, string opcodestr>
     : RVInstIBase<0b010, OPC_OP_IMM_32, (outs GPR:$rd), (ins GPR:$rs1),
@@ -277,6 +353,15 @@ class RVPUnary_ri<bits<2> w, bits<5> uf, string opcodestr>
   let Inst{24-20} = uf;
 }
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPPairUnary_r<bits<2> w, bits<5> uf, string opcodestr>
+    : RVPPairBase<0b110, 0b0, 0b0, (outs GPRPairRV32:$rd),
+                  (ins GPRPairRV32:$rs1), opcodestr, "$rd, $rs1"> {
+  let Inst{31}    = 0b0;
+  let Inst{26-25} = w;
+  let Inst{24-20} = uf;
+}
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class RVPBinaryScalar_rr<bits<3> f, bits<2> w, bits<3> funct3, string opcodestr>
     : RVInstRBase<funct3, OPC_OP_IMM_32, (outs GPR:$rd),
@@ -314,6 +399,22 @@ class RVPNarrowingBinary_rr<bits<3> f, bits<2> w, string opcodestr>
   let Inst{24-20} = rs2;
 }
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPPairBinary_rr<bits<4> f, bits<2> w, string opcodestr>
+  : RVPPairBinaryBase_rr<f{3-1}, f{0}, w, 0b0, 0b0, opcodestr>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPPairBinaryShift_rr<bits<3> f, bits<2> w, string opcodestr>
+    : RVPPairBinaryBase_rr<f, 0b0, w, 0b1, 0b0, opcodestr>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPPairBinaryPack_rr<bits<3> f, bits<2> w, string opcodestr>
+    : RVPPairBinaryBase_rr<f, 0b0, w, 0b0, 0b1, opcodestr>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class RVPPairBinaryExchanged_rr<bits<4> f, bits<2> w, string opcodestr>
+    : RVPPairBinaryBase_rr<f{3-1}, f{0}, w, 0b1, 0b1, opcodestr>;
+
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
 class RVPTernary_rrr<bits<4> f, bits<2> w, bits<3> funct3, string opcodestr>
     : RVInstRBase<funct3, OPC_OP_32, (outs GPR:$rd_wb),
@@ -1196,4 +1297,161 @@ let Predicates = [HasStdExtP, IsRV32] in {
   def PNCLIPR_BS   : RVPNarrowingShift_rr<0b111, 0b00, "pnclipr.bs">;
   def PNCLIPR_HS   : RVPNarrowingShift_rr<0b111, 0b01, "pnclipr.hs">;
   def NCLIPR       : RVPNarrowingShift_rr<0b111, 0b11, "nclipr">;
+
+  def PSLLI_DB      : RVPPairShiftB_ri<0b000,  "pslli.db">;
+  def PSLLI_DH      : RVPPairShiftH_ri<0b000, "pslli.dh">;
+  def PSLLI_DW      : RVPPairShiftW_ri<0b000, "pslli.dw">;
+
+  def PSSLAI_DH     : RVPPairShiftH_ri<0b101, "psslai.dh">;
+  def PSSLAI_DW     : RVPPairShiftW_ri<0b101, "psslai.dw">;
+
+  def PSEXT_DH_B    : RVPPairUnary_r<0b00, 0b00100, "psext.dh.b">;
+  def PSEXT_DW_B    : RVPPairUnary_r<0b01, 0b00100, "psext.dw.b">;
+
+  def PSEXT_DW_H    : RVPPairUnary_r<0b01, 0b00101, "psext.dw.h">;
+
+  def PSABS_DH      : RVPPairUnary_r<0b00, 0b00111, "psabs.dh">;
+  def PSABS_DB      : RVPPairUnary_r<0b10, 0b00111, "psabs.db">;
+
+  def PSLL_DHS      : RVPPairShift_rr<0b000, 0b00, "psll.dhs">;
+  def PSLL_DWS      : RVPPairShift_rr<0b000, 0b01, "psll.dws">;
+  def PSLL_DBS      : RVPPairShift_rr<0b000, 0b10, "psll.dbs">;
+
+  def PADD_DHS      : RVPPairShift_rr<0b001, 0b00, "padd.dhs">;
+  def PADD_DWS      : RVPPairShift_rr<0b001, 0b01, "padd.dws">;
+  def PADD_DBS      : RVPPairShift_rr<0b001, 0b10, "padd.dbs">;
+
+  def PSSHA_DHS     : RVPPairShift_rr<0b110, 0b00, "pssha.dhs">;
+  def PSSHA_DWS     : RVPPairShift_rr<0b110, 0b01, "pssha.dws">;
+
+  def PSSHAR_DHS    : RVPPairShift_rr<0b111, 0b00, "psshar.dhs">;
+  def PSSHAR_DWS    : RVPPairShift_rr<0b111, 0b01, "psshar.dws">;
+
+  def PSRLI_DB      : RVPPairShiftB_ri<0b000, "psrli.db",  0b1>;
+  def PSRLI_DH      : RVPPairShiftH_ri<0b000, "psrli.dh",  0b1>;
+  def PSRLI_DW      : RVPPairShiftW_ri<0b000, "psrli.dw",  0b1>;
+
+  def PUSATI_DH     : RVPPairShiftH_ri<0b010, "pusati.dh", 0b1>;
+  def PUSATI_DW     : RVPPairShiftW_ri<0b010, "pusati.dw", 0b1>;
+
+  def PSRAI_DB      : RVPPairShiftB_ri<0b100, "psrai.db",  0b1>;
+  def PSRAI_DH      : RVPPairShiftH_ri<0b100, "psrai.dh",  0b1>;
+  def PSRAI_DW      : RVPPairShiftW_ri<0b100, "psrai.dw",  0b1>;
+
+  def PSRARI_DH     : RVPPairShiftH_ri<0b101, "psrari.dh", 0b1>;
+  def PSRARI_DW     : RVPPairShiftW_ri<0b101, "psrari.dw", 0b1>;
+
+  def PSATI_DH      : RVPPairShiftH_ri<0b110, "psati.dh",  0b1>;
+  def PSATI_DW      : RVPPairShiftW_ri<0b110, "psati.dw",  0b1>;
+
+  def PSRL_DHS      : RVPPairShift_rr<0b000, 0b00, "psrl.dhs", 0b1>;
+  def PSRL_DWS      : RVPPairShift_rr<0b000, 0b01, "psrl.dws", 0b1>;
+  def PSRL_DBS      : RVPPairShift_rr<0b000, 0b10, "psrl.dbs", 0b1>;
+
+  def PSRA_DHS      : RVPPairShift_rr<0b100, 0b00, "psra.dhs", 0b1>;
+  def PSRA_DWS      : RVPPairShift_rr<0b100, 0b01, "psra.dws", 0b1>;
+  def PSRA_DBS      : RVPPairShift_rr<0b100, 0b10, "psra.dbs", 0b1>;
+
+  def PADD_DH       : RVPPairBinary_rr<0b0000, 0b00, "padd.dh">;
+  def PADD_DW       : RVPPairBinary_rr<0b0000, 0b01, "padd.dw">;
+  def PADD_DB       : RVPPairBinary_rr<0b0000, 0b10, "padd.db">;
+  def ADDD          : RVPPairBinary_rr<0b0000, 0b11, "addd">;
+
+  def PSADD_DH      : RVPPairBinary_rr<0b0010, 0b00, "psadd.dh">;
+  def PSADD_DW      : RVPPairBinary_rr<0b0010, 0b01, "psadd.dw">;
+  def PSADD_DB      : RVPPairBinary_rr<0b0010, 0b10, "psadd.db">;
+
+  def PAADD_DH      : RVPPairBinary_rr<0b0011, 0b00, "paadd.dh">;
+  def PAADD_DW      : RVPPairBinary_rr<0b0011, 0b01, "paadd.dw">;
+  def PAADD_DB      : RVPPairBinary_rr<0b0011, 0b10, "paadd.db">;
+
+  def PSADDU_DH     : RVPPairBinary_rr<0b0110, 0b00, "psaddu.dh">;
+  def PSADDU_DW     : RVPPairBinary_rr<0b0110, 0b01, "psaddu.dw">;
+  def PSADDU_DB     : RVPPairBinary_rr<0b0110, 0b10, "psaddu.db">;
+
+  def PAADDU_DH     : RVPPairBinary_rr<0b0111, 0b00, "paaddu.dh">;
+  def PAADDU_DW     : RVPPairBinary_rr<0b0111, 0b01, "paaddu.dw">;
+  def PAADDU_DB     : RVPPairBinary_rr<0b0111, 0b10, "paaddu.db">;
+
+  def PSUB_DH       : RVPPairBinary_rr<0b1000, 0b00, "psub.dh">;
+  def PSUB_DW       : RVPPairBinary_rr<0b1000, 0b01, "psub.dw">;
+  def PSUB_DB       : RVPPairBinary_rr<0b1000, 0b10, "psub.db">;
+  def SUBD          : RVPPairBinary_rr<0b1000, 0b11, "subd">;
+
+  def PDIF_DH       : RVPPairBinary_rr<0b1001, 0b00, "pdif.dh">;
+  def PDIF_DB       : RVPPairBinary_rr<0b1001, 0b10, "pdif.db">;
+
+  def PSSUB_DH      : RVPPairBinary_rr<0b1010, 0b00, "pssub.dh">;
+  def PSSUB_DW      : RVPPairBinary_rr<0b1010, 0b01, "pssub.dw">;
+  def PSSUB_DB      : RVPPairBinary_rr<0b1010, 0b10, "pssub.db">;
+
+  def PASUB_DH      : RVPPairBinary_rr<0b1011, 0b00, "pasub.dh">;
+  def PASUB_DW      : RVPPairBinary_rr<0b1011, 0b01, "pasub.dw">;
+  def PASUB_DB      : RVPPairBinary_rr<0b1011, 0b10, "pasub.db">;
+
+  def PDIFU_DH      : RVPPairBinary_rr<0b1101, 0b00, "pdifu.dh">;
+  def PDIFU_DB      : RVPPairBinary_rr<0b1101, 0b10, "pdifu.db">;
+
+  def PSSUBU_DH     : RVPPairBinary_rr<0b1110, 0b00, "pssubu.dh">;
+  def PSSUBU_DW     : RVPPairBinary_rr<0b1110, 0b01, "pssubu.dw">;
+  def PSSUBU_DB     : RVPPairBinary_rr<0b1110, 0b10, "pssubu.db">;
+
+  def PASUBU_DH     : RVPPairBinary_rr<0b1111, 0b00, "pasubu.dh">;
+  def PASUBU_DW     : RVPPairBinary_rr<0b1111, 0b01, "pasubu.dw">;
+  def PASUBU_DB     : RVPPairBinary_rr<0b1111, 0b10, "pasubu.db">;
+
+  def PSH1ADD_DH    : RVPPairBinaryShift_rr<0b010, 0b00, "psh1add.dh">;
+  def PSH1ADD_DW    : RVPPairBinaryShift_rr<0b010, 0b01, "psh1add.dw">;
+
+  def PSSH1SADD_DH  : RVPPairBinaryShift_rr<0b011, 0b00, "pssh1sadd.dh">;
+  def PSSH1SADD_DW  : RVPPairBinaryShift_rr<0b011, 0b01, "pssh1sadd.dw">;
+
+  def PPACK_DH      : RVPPairBinaryPack_rr<0b000, 0b00, "ppack.dh">;
+  def PPACK_DW      : RVPPairBinaryPack_rr<0b000, 0b01, "ppack.dw">;
+
+  def PPACKBT_DH    : RVPPairBinaryPack_rr<0b001, 0b00, "ppackbt.dh">;
+  def PPACKBT_DW    : RVPPairBinaryPack_rr<0b001, 0b01, "ppackbt.dw">;
+
+  def PPACKTB_DH    : RVPPairBinaryPack_rr<0b010, 0b00, "ppacktb.dh">;
+  def PPACKTB_DW    : RVPPairBinaryPack_rr<0b010, 0b01, "ppacktb.dw">;
+
+  def PPACKT_DH     : RVPPairBinaryPack_rr<0b011, 0b00, "ppackt.dh">;
+  def PPACKT_DW     : RVPPairBinaryPack_rr<0b011, 0b01, "ppackt.dw">;
+
+  def PAS_DHX       : RVPPairBinaryExchanged_rr<0b0000, 0b00, "pas.dhx">;
+  def PSA_DHX       : RVPPairBinaryExchanged_rr<0b0000, 0b10, "psa.dhx">;
+
+  def PSAS_DHX      : RVPPairBinaryExchanged_rr<0b0010, 0b00, "psas.dhx">;
+  def PSSA_DHX      : RVPPairBinaryExchanged_rr<0b0010, 0b10, "pssa.dhx">;
+
+  def PAAX_DHX      : RVPPairBinaryExchanged_rr<0b0011, 0b00, "paax.dhx">;
+  def PASA_DHX      : RVPPairBinaryExchanged_rr<0b0011, 0b10, "pasa.dhx">;
+
+  def PMSEQ_DH      : RVPPairBinaryExchanged_rr<0b1000, 0b00, "pmseq.dh">;
+  def PMSEQ_DW      : RVPPairBinaryExchanged_rr<0b1000, 0b01, "pmseq.dw">;
+  def PMSEQ_DB      : RVPPairBinaryExchanged_rr<0b1000, 0b10, "pmseq.db">;
+
+  def PMSLT_DH      : RVPPairBinaryExchanged_rr<0b1010, 0b00, "pmslt.dh">;
+  def PMSLT_DW      : RVPPairBinaryExchanged_rr<0b1010, 0b01, "pmslt.dw">;
+  def PMSLT_DB      : RVPPairBinaryExchanged_rr<0b1010, 0b10, "pmslt.db">;
+
+  def PMSLTU_DH     : RVPPairBinaryExchanged_rr<0b1011, 0b00, "pmsltu.dh">;
+  def PMSLTU_DW     : RVPPairBinaryExchanged_rr<0b1011, 0b01, "pmsltu.dw">;
+  def PMSLTU_DB     : RVPPairBinaryExchanged_rr<0b1011, 0b10, "pmsltu.db">;
+
+  def PMIN_DH       : RVPPairBinaryExchanged_rr<0b1100, 0b00, "pmin.dh">;
+  def PMIN_DW       : RVPPairBinaryExchanged_rr<0b1100, 0b01, "pmin.dw">;
+  def PMIN_DB       : RVPPairBinaryExchanged_rr<0b1100, 0b10, "pmin.db">;
+
+  def PMINU_DH      : RVPPairBinaryExchanged_rr<0b1101, 0b00, "pminu.dh">;
+  def PMINU_DW      : RVPPairBinaryExchanged_rr<0b1101, 0b01, "pminu.dw">;
+  def PMINU_DB      : RVPPairBinaryExchanged_rr<0b1101, 0b10, "pminu.db">;
+
+  def PMAX_DH       : RVPPairBinaryExchanged_rr<0b1110, 0b00, "pmax.dh">;
+  def PMAX_DW       : RVPPairBinaryExchanged_rr<0b1110, 0b01, "pmax.dw">;
+  def PMAX_DB       : RVPPairBinaryExchanged_rr<0b1110, 0b10, "pmax.db">;
+
+  def PMAXU_DH      : RVPPairBinaryExchanged_rr<0b1111, 0b00, "pmaxu.dh">;
+  def PMAXU_DW      : RVPPairBinaryExchanged_rr<0b1111, 0b01, "pmaxu.dw">;
+  def PMAXU_DB      : RVPPairBinaryExchanged_rr<0b1111, 0b10, "pmaxu.db">;
 } // Predicates = [HasStdExtP, IsRV32]
diff --git a/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s b/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s
index c5c0d2f3a0b12..8e8c42e033b8a 100644
--- a/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s
+++ b/llvm/test/MC/RISCV/invalid-instruction-spellcheck.s
@@ -22,10 +22,10 @@ fl ft0, 0(sp)
 # CHECK-RV64IF: did you mean: flw, la, lb, ld, lh, li, lw
 # CHECK-NEXT: fl ft0, 0(sp)
 
-addd x1, x1, x1
+addc x1, x1, x1
 # CHECK-RV32: did you mean: add, addi
 # CHECK-RV64: did you mean: add, addi, addw
-# CHECK-NEXT: addd x1, x1, x1
+# CHECK-NEXT: addc x1, x1, x1
 
 vm x0, x0
 # CHECK: did you mean: mv
diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s
index cd36fa3069e12..3a41d0d237c2e 100644
--- a/llvm/test/MC/RISCV/rv32p-valid.s
+++ b/llvm/test/MC/RISCV/rv32p-valid.s
@@ -1017,3 +1017,342 @@ pnclipr.hs a4, s2, t3
 # CHECK-ASM-AND-OBJ: nclipr t1, t5, a2
 # CHECK-ASM: encoding: [0x1b,0xc3,0xcf,0x7e]
 nclipr t1, t5, a2
+# CHECK-ASM-AND-OBJ: pslli.db a0, s2, 0
+# CHECK-ASM: encoding: [0x1b,0x65,0x89,0x00]
+pslli.db a0, s2, 0
+# CHECK-ASM-AND-OBJ: pslli.dh t3, t1, 2
+# CHECK-ASM: encoding: [0x1b,0x6e,0x23,0x01]
+pslli.dh t3, t1, 2
+# CHECK-ASM-AND-OBJ: pslli.dw a4, t3, 1
+# CHECK-ASM: encoding: [0x1b,0x67,0x1e,0x02]
+pslli.dw a4, t3, 1
+# CHECK-ASM-AND-OBJ: psslai.dh t1, a4, 3
+# CHECK-ASM: encoding: [0x1b,0x63,0x37,0x51]
+psslai.dh t1, a4, 3
+# CHECK-ASM-AND-OBJ: psslai.dw a0, t3, 5
+# CHECK-ASM: encoding: [0x1b,0x65,0x5e,0x52]
+psslai.dw a0, t3, 5
+# CHECK-ASM-AND-OBJ: psext.dh.b t1, t5
+# CHECK-ASM: encoding: [0x1b,0x63,0x4f,0x60]
+psext.dh.b t1, t5
+# CHECK-ASM-AND-OBJ: psext.dw.b t5, t5
+# CHECK-ASM: encoding: [0x1b,0x6f,0x4f,0x62]
+psext.dw.b t5, t5
+# CHECK-ASM-AND-OBJ: psext.dw.h s0, t1
+# CHECK-ASM: encoding: [0x1b,0x64,0x53,0x62]
+psext.dw.h s0, t1
+# CHECK-ASM-AND-OBJ: psabs.dh s0, s2
+# CHECK-ASM: encoding: [0x1b,0x64,0x79,0x60]
+psabs.dh s0, s2
+# CHECK-ASM-AND-OBJ: psabs.db s2, a2
+# CHECK-ASM: encoding: [0x1b,0x69,0x76,0x64]
+psabs.db s2, a2
+# CHECK-ASM-AND-OBJ: psll.dhs s2, t3, a4
+# CHECK-ASM: encoding: [0x1b,0x69,0xee,0x08]
+psll.dhs s2, t3, a4
+# CHECK-ASM-AND-OBJ: psll.dws a2, t1, t3
+# CHECK-ASM: encoding: [0x1b,0x66,0xc3,0x0b]
+psll.dws a2, t1, t3
+# CHECK-ASM-AND-OBJ: psll.dbs a0, a4, a2
+# CHECK-ASM: encoding: [0x1b,0x65,0xc7,0x0c]
+psll.dbs a0, a4, a2
+# CHECK-ASM-AND-OBJ: padd.dhs t1, a4, s2
+# CHECK-ASM: encoding: [0x1b,0x63,0x27,0x19]
+padd.dhs t1, a4, s2
+# CHECK-ASM-AND-OBJ: padd.dws a4, a4, t3
+# CHECK-ASM: encoding: [0x1b,0x67,0xc7,0x1b]
+padd.dws a4, a4, t3
+# CHECK-ASM-AND-OBJ: padd.dbs a2, a4, t3
+# CHECK-ASM: encoding: [0x1b,0x66,0xc7,0x1d]
+padd.dbs a2, a4, t3
+# CHECK-ASM-AND-OBJ: pssha.dhs a0, s0, s2
+# CHECK-ASM: encoding: [0x1b,0x65,0x24,0x69]
+pssha.dhs a0, s0, s2
+# CHECK-ASM-AND-OBJ: pssha.dws a0, t1, s2
+# CHECK-ASM: encoding: [0x1b,0x65,0x23,0x6b]
+pssha.dws a0, t1, s2
+# CHECK-ASM-AND-OBJ: psshar.dhs a2, a4, t3
+# CHECK-ASM: encoding: [0x1b,0x66,0xc7,0x79]
+psshar.dhs a2, a4, t3
+# CHECK-ASM-AND-OBJ: psshar.dws s0, t3, s0
+# CHECK-ASM: encoding: [0x1b,0x64,0x8e,0x7a]
+psshar.dws s0, t3, s0
+# CHECK-ASM-AND-OBJ: psrli.db t5, a2, 0
+# CHECK-ASM: encoding: [0x1b,0xef,0x86,0x00]
+psrli.db t5, a2, 0
+# CHECK-ASM-AND-OBJ: psrli.dh a2, t3, 1
+# CHECK-ASM: encoding: [0x1b,0xe6,0x1e,0x01]
+psrli.dh a2, t3, 1
+# CHECK-ASM-AND-OBJ: psrli.dw s2, t1, 3
+# CHECK-ASM: encoding: [0x1b,0xe9,0x33,0x02]
+psrli.dw s2, t1, 3
+# CHECK-ASM-AND-OBJ: pusati.dh a0, a4, 5
+# CHECK-ASM: encoding: [0x1b,0xe5,0x57,0x21]
+pusati.dh a0, a4, 5
+# CHECK-ASM-AND-OBJ: pusati.dw a0, s2, 7
+# CHECK-ASM: encoding: [0x1b,0xe5,0x79,0x22]
+pusati.dw a0, s2, 7
+# CHECK-ASM-AND-OBJ: psrai.db t5, t5, 1
+# CHECK-ASM: encoding: [0x1b,0xef,0x9f,0x40]
+psrai.db t5, t5, 1
+# CHECK-ASM-AND-OBJ: psrai.dh s0, a2, 5
+# CHECK-ASM: encoding: [0x1b,0xe4,0x56,0x41]
+psrai.dh s0, a2, 5
+# CHECK-ASM-AND-OBJ: psrai.dw t5, a0, 9
+# CHECK-ASM: encoding: [0x1b,0xef,0x95,0x42]
+psrai.dw t5, a0, 9
+# CHECK-ASM-AND-OBJ: psrari.dh a2, a2, 6
+# CHECK-ASM: encoding: [0x1b,0xe6,0x66,0x51]
+psrari.dh a2, a2, 6
+# CHECK-ASM-AND-OBJ: psrari.dw a4, a0, 5
+# CHECK-ASM: encoding: [0x1b,0xe7,0x55,0x52]
+psrari.dw a4, a0, 5
+# CHECK-ASM-AND-OBJ: psati.dh s2, s2, 9
+# CHECK-ASM: encoding: [0x1b,0xe9,0x99,0x61]
+psati.dh s2, s2, 9
+# CHECK-ASM-AND-OBJ: psati.dw t5, t3, 14
+# CHECK-ASM: encoding: [0x1b,0xef,0xee,0x62]
+psati.dw t5, t3, 14
+# CHECK-ASM-AND-OBJ: psrl.dhs a0, t1, t5
+# CHECK-ASM: encoding: [0x1b,0xe5,0xe3,0x09]
+psrl.dhs a0, t1, t5
+# CHECK-ASM-AND-OBJ: psrl.dws s0, s2, t1
+# CHECK-ASM: encoding: [0x1b,0xe4,0x69,0x0a]
+psrl.dws s0, s2, t1
+# CHECK-ASM-AND-OBJ: psrl.dbs a0, s0, t5
+# CHECK-ASM: encoding: [0x1b,0xe5,0xe4,0x0d]
+psrl.dbs a0, s0, t5
+# CHECK-ASM-AND-OBJ: psra.dhs a4, t3, t1
+# CHECK-ASM: encoding: [0x1b,0xe7,0x6e,0x48]
+psra.dhs a4, t3, t1
+# CHECK-ASM-AND-OBJ: psra.dws a2, s2, t1
+# CHECK-ASM: encoding: [0x1b,0xe6,0x69,0x4a]
+psra.dws a2, s2, t1
+# CHECK-ASM-AND-OBJ: psra.dbs s0, t1, t5
+# CHECK-ASM: encoding: [0x1b,0xe4,0xe3,0x4d]
+psra.dbs s0, t1, t5
+# CHECK-ASM-AND-OBJ: padd.dh s2, a4, a2
+# CHECK-ASM: encoding: [0x1b,0x69,0xc7,0x80]
+padd.dh s2, a4, a2
+# CHECK-ASM-AND-OBJ: padd.dw a2, s2, a2
+# CHECK-ASM: encoding: [0x1b,0x66,0xc9,0x82]
+padd.dw a2, s2, a2
+# CHECK-ASM-AND-OBJ: padd.db a4, a2, a2
+# CHECK-ASM: encoding: [0x1b,0x67,0xc6,0x84]
+padd.db a4, a2, a2
+# CHECK-ASM-AND-OBJ: addd t1, s2, s0
+# CHECK-ASM: encoding: [0x1b,0x63,0x89,0x86]
+addd t1, s2, s0
+# CHECK-ASM-AND-OBJ: psadd.dh t3, s2, t3
+# CHECK-ASM: encoding: [0x1b,0x6e,0xc9,0x91]
+psadd.dh t3, s2, t3
+# CHECK-ASM-AND-OBJ: psadd.dw a4, t3, t3
+# CHECK-ASM: encoding: [0x1b,0x67,0xce,0x93]
+psadd.dw a4, t3, t3
+# CHECK-ASM-AND-OBJ: psadd.db t5, s0, a2
+# CHECK-ASM: encoding: [0x1b,0x6f,0xc4,0x94]
+psadd.db t5, s0, a2
+# CHECK-ASM-AND-OBJ: paadd.dh t1, s2, a0
+# CHECK-ASM: encoding: [0x1b,0x63,0xa9,0x98]
+paadd.dh t1, s2, a0
+# CHECK-ASM-AND-OBJ: paadd.dw a4, a2, s0
+# CHECK-ASM: encoding: [0x1b,0x67,0x86,0x9a]
+paadd.dw a4, a2, s0
+# CHECK-ASM-AND-OBJ: paadd.db t5, t3, s0
+# CHECK-ASM: encoding: [0x1b,0x6f,0x8e,0x9c]
+paadd.db t5, t3, s0
+# CHECK-ASM-AND-OBJ: psaddu.dh a4, a2, t5
+# CHECK-ASM: encoding: [0x1b,0x67,0xe6,0xb1]
+psaddu.dh a4, a2, t5
+# CHECK-ASM-AND-OBJ: psaddu.dw a4, t5, s2
+# CHECK-ASM: encoding: [0x1b,0x67,0x2f,0xb3]
+psaddu.dw a4, t5, s2
+# CHECK-ASM-AND-OBJ: psaddu.db a4, a0, t1
+# CHECK-ASM: encoding: [0x1b,0x67,0x65,0xb4]
+psaddu.db a4, a0, t1
+# CHECK-ASM-AND-OBJ: paaddu.dh a4, a4, s2
+# CHECK-ASM: encoding: [0x1b,0x67,0x27,0xb9]
+paaddu.dh a4, a4, s2
+# CHECK-ASM-AND-OBJ: paaddu.dw t3, s0, t5
+# CHECK-ASM: encoding: [0x1b,0x6e,0xe4,0xbb]
+paaddu.dw t3, s0, t5
+# CHECK-ASM-AND-OBJ: paaddu.db a0, s0, s0
+# CHECK-ASM: encoding: [0x1b,0x65,0x84,0xbc]
+paaddu.db a0, s0, s0
+# CHECK-ASM-AND-OBJ: psub.dh t5, a4, a4
+# CHECK-ASM: encoding: [0x1b,0x6f,0xe7,0xc0]
+psub.dh t5, a4, a4
+# CHECK-ASM-AND-OBJ: psub.dw t1, s0, t5
+# CHECK-ASM: encoding: [0...
[truncated]

topperc
topperc approved these changes Sep 17, 2025
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LGTM

@realqhc @topperc
Remove excess space
33c245a 
Co-authored-by: Craig Topper <craig.topper@sifive.com>
@realqhc realqhc merged commit dd92609 into llvm:main Sep 19, 2025
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@realqhc realqhc deleted the p-remaining branch September 19, 2025 03:08
SeongjaeP pushed a commit to SeongjaeP/llvm-project that referenced this pull request Sep 23, 2025
@realqhc @topperc @SeongjaeP
[RISC-V] Add P-ext MC Support for Remaining Pair Operations (llvm#159247
4121631 
)

This patch implements pages 21-24 from jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf

Documentation:
jhauser.us/RISCV/ext-P/RVP-baseInstrs-014.pdf
jhauser.us/RISCV/ext-P/RVP-instrEncodings-015.pdf

Co-authored-by: Craig Topper <craig.topper@sifive.com>
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