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[PowerPC] Add custom lowering for SADD overflow for i32 and i64 #159255

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[PowerPC] Add custom lowering for SADD overflow for i32 and i64 #159255

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8e3f617
[PowerPC] Add custom lowering for SADD overflow for i32 and i64
AditiRM Sep 17, 2025
f773ead
[nit] fix formating
AditiRM Sep 17, 2025
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32 changes: 31 additions & 1 deletion llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -204,8 +204,11 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
// setbc instruction.
if (!Subtarget.hasP10Vector()) {
setOperationAction(ISD::SSUBO, MVT::i32, Custom);
if (isPPC64)
setOperationAction(ISD::SADDO, MVT::i32, Custom);
if (isPPC64) {
setOperationAction(ISD::SSUBO, MVT::i64, Custom);
setOperationAction(ISD::SADDO, MVT::i64, Custom);
}
}

// Match BITREVERSE to customized fast code sequence in the td file.
Expand Down Expand Up @@ -12614,6 +12617,31 @@ SDValue PPCTargetLowering::LowerSSUBO(SDValue Op, SelectionDAG &DAG) const {
return DAG.getMergeValues({Sub, OverflowTrunc}, dl);
}

SDValue PPCTargetLowering::LowerSADDO(SDValue Op, SelectionDAG &DAG) const {

SDLoc dl(Op);
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
EVT VT = Op.getNode()->getValueType(0);

SDValue Add = DAG.getNode(ISD::ADD, dl, VT, LHS, RHS);

SDValue Xor1 = DAG.getNode(ISD::XOR, dl, VT, LHS, RHS);
SDValue NotXor1 = DAG.getNOT(dl, Xor1, VT);
SDValue Xor2 = DAG.getNode(ISD::XOR, dl, VT, Add, LHS);

SDValue And = DAG.getNode(ISD::AND, dl, VT, NotXor1, Xor2);

SDValue Overflow =
DAG.getNode(ISD::SRL, dl, VT, And,
DAG.getConstant(VT.getSizeInBits() - 1, dl, MVT::i32));

SDValue OverflowTrunc =
DAG.getNode(ISD::TRUNCATE, dl, Op.getNode()->getValueType(1), Overflow);

return DAG.getMergeValues({Add, OverflowTrunc}, dl);
}

/// LowerOperation - Provide custom lowering hooks for some operations.
///
SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
Expand All @@ -12638,6 +12666,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
case ISD::SSUBO:
return LowerSSUBO(Op, DAG);
case ISD::SADDO:
return LowerSADDO(Op, DAG);

case ISD::INLINEASM:
case ISD::INLINEASM_BR: return LowerINLINEASM(Op, DAG);
Expand Down
1 change: 1 addition & 0 deletions llvm/lib/Target/PowerPC/PPCISelLowering.h
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Expand Up @@ -1283,6 +1283,7 @@ namespace llvm {
SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSSUBO(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSADDO(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerINLINEASM(SDValue Op, SelectionDAG &DAG) const;
Expand Down
22 changes: 10 additions & 12 deletions llvm/test/CodeGen/PowerPC/saddo-ssubo.ll
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Expand Up @@ -49,12 +49,11 @@ entry:
define i1 @test_saddo_i32(i32 %a, i32 %b) nounwind {
; CHECK-LABEL: test_saddo_i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add 5, 3, 4
; CHECK-NEXT: cmpwi 1, 4, 0
; CHECK-NEXT: cmpw 5, 3
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: creqv 20, 4, 0
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: xor 5, 3, 4
; CHECK-NEXT: add 4, 3, 4
; CHECK-NEXT: xor 3, 4, 3
; CHECK-NEXT: andc 3, 3, 5
; CHECK-NEXT: srwi 3, 3, 31
; CHECK-NEXT: blr
entry:
%res = call { i32, i1 } @llvm.sadd.with.overflow.i32(i32 %a, i32 %b) nounwind
Expand All @@ -65,12 +64,11 @@ entry:
define i1 @test_saddo_i64(i64 %a, i64 %b) nounwind {
; CHECK-LABEL: test_saddo_i64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: add 5, 3, 4
; CHECK-NEXT: cmpdi 1, 4, 0
; CHECK-NEXT: cmpd 5, 3
; CHECK-NEXT: li 3, 1
; CHECK-NEXT: creqv 20, 4, 0
; CHECK-NEXT: isel 3, 0, 3, 20
; CHECK-NEXT: xor 5, 3, 4
; CHECK-NEXT: add 4, 3, 4
; CHECK-NEXT: xor 3, 4, 3
; CHECK-NEXT: andc 3, 3, 5
; CHECK-NEXT: rldicl 3, 3, 1, 63
; CHECK-NEXT: blr
entry:
%res = call { i64, i1 } @llvm.sadd.with.overflow.i64(i64 %a, i64 %b) nounwind
Expand Down