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AMDGPU: Fixes for regbankselecting copies of i1 physregs to sgprs #159283

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Merged
merged 2 commits into from
Sep 17, 2025
Merged

AMDGPU: Fixes for regbankselecting copies of i1 physregs to sgprs #159283

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0700ddd
GlobalISel: Relax verifier between physreg and typed vreg
arsenm Sep 17, 2025
1926bc3
AMDGPU: Fixes for regbankselecting copies of i1 physregs to sgprs
arsenm Sep 17, 2025
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16 changes: 10 additions & 6 deletions llvm/lib/CodeGen/MachineVerifier.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -2376,20 +2376,24 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {

// If we have only one valid type, this is likely a copy between a virtual
// and physical register.
TypeSize SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
TypeSize DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
TypeSize SrcSize = TypeSize::getZero();
TypeSize DstSize = TypeSize::getZero();
if (SrcReg.isPhysical() && DstTy.isValid()) {
const TargetRegisterClass *SrcRC =
TRI->getMinimalPhysRegClassLLT(SrcReg, DstTy);
if (SrcRC)
SrcSize = TRI->getRegSizeInBits(*SrcRC);
if (!SrcRC)
SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
} else {
SrcSize = TRI->getRegSizeInBits(SrcReg, *MRI);
}

if (DstReg.isPhysical() && SrcTy.isValid()) {
const TargetRegisterClass *DstRC =
TRI->getMinimalPhysRegClassLLT(DstReg, SrcTy);
if (DstRC)
DstSize = TRI->getRegSizeInBits(*DstRC);
if (!DstRC)
DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
} else {
DstSize = TRI->getRegSizeInBits(DstReg, *MRI);
}

// The next two checks allow COPY between physical and virtual registers,
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14 changes: 10 additions & 4 deletions llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
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Expand Up @@ -3845,21 +3845,27 @@ AMDGPURegisterBankInfo::getInstrMapping(const MachineInstr &MI) const {
// want the most straightforward mapping, so just directly handle this.
const RegisterBank *DstBank = getRegBank(DstReg, MRI, *TRI);
const RegisterBank *SrcBank = getRegBank(SrcReg, MRI, *TRI);
assert(SrcBank && "src bank should have been assigned already");

// For COPY between a physical reg and an s1, there is no type associated so
// we need to take the virtual register's type as a hint on how to interpret
// s1 values.
unsigned Size;
if (!SrcReg.isVirtual() && !DstBank &&
MRI.getType(DstReg) == LLT::scalar(1))
MRI.getType(DstReg) == LLT::scalar(1)) {
DstBank = &AMDGPU::VCCRegBank;
else if (!DstReg.isVirtual() && MRI.getType(SrcReg) == LLT::scalar(1))
Size = 1;
} else if (!DstReg.isVirtual() && MRI.getType(SrcReg) == LLT::scalar(1)) {
DstBank = &AMDGPU::VCCRegBank;
Size = 1;
} else {
Size = getSizeInBits(DstReg, MRI, *TRI);
}

if (!DstBank)
DstBank = SrcBank;
else if (!SrcBank)
SrcBank = DstBank;

unsigned Size = getSizeInBits(DstReg, MRI, *TRI);
if (MI.getOpcode() != AMDGPU::G_FREEZE &&
cannotCopy(*DstBank, *SrcBank, TypeSize::getFixed(Size)))
return getInvalidInstructionMapping();
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