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[TableGen][DecoderEmitter] Inline insertBits() (NFC) #159353

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Sep 17, 2025
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[TableGen][DecoderEmitter] Inline insertBits() (NFC) #159353

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[TableGen][DecoderEmitter] Inline `insertBits()` (NFC)
s-barannikov Sep 17, 2025
48dac25
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s-barannikov Sep 17, 2025
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14 changes: 0 additions & 14 deletions llvm/include/llvm/MC/MCDecoder.h
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Original file line number Diff line number Diff line change
Expand Up @@ -58,20 +58,6 @@ uint64_t fieldFromInstruction(const std::bitset<N> &Insn, unsigned StartBit,
return ((Insn >> StartBit) & Mask).to_ullong();
}

// Helper function for inserting bits extracted from an encoded instruction into
// an integer-typed field.
template <typename IntType>
static std::enable_if_t<std::is_integral_v<IntType>, void>
insertBits(IntType &field, IntType bits, unsigned startBit, unsigned numBits) {
// Check that no bit beyond numBits is set, so that a simple bitwise |
// is sufficient.
assert((~(((IntType)1 << numBits) - 1) & bits) == 0 &&
"bits has more than numBits bits set");
assert(startBit + numBits <= sizeof(IntType) * 8);
(void)numBits;
field |= bits << startBit;
}

} // namespace llvm::MCD

#endif // LLVM_MC_MCDECODER_H
4 changes: 2 additions & 2 deletions llvm/test/TableGen/BitOffsetDecoder.td
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Expand Up @@ -59,6 +59,6 @@ def baz : Instruction {

// CHECK: tmp = fieldFromInstruction(insn, 8, 7);
// CHECK: tmp = fieldFromInstruction(insn, 8, 8) << 3;
// CHECK: insertBits(tmp, fieldFromInstruction(insn, 8, 4), 7, 4);
// CHECK: insertBits(tmp, fieldFromInstruction(insn, 12, 4), 3, 4);
// CHECK: tmp |= fieldFromInstruction(insn, 8, 4) << 7;
// CHECK: tmp |= fieldFromInstruction(insn, 12, 4) << 3;
// CHECK: tmp = fieldFromInstruction(insn, 8, 8) << 4;
4 changes: 2 additions & 2 deletions llvm/test/TableGen/DecoderEmitter/VarLenDecoder.td
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Expand Up @@ -81,8 +81,8 @@ def FOO32 : MyVarInst<MemOp32> {
// CHECK-NEXT: tmp = fieldFromInstruction(insn, 0, 3);
// CHECK-NEXT: if (!Check(S, myCustomDecoder(MI, tmp, Address, Decoder))) { return MCDisassembler::Fail; }
// CHECK-NEXT: tmp = 0x0;
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 11, 16), 16, 16);
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 27, 16), 0, 16);
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 11, 16) << 16;
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 27, 16);
// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
// CHECK-NEXT: return S;

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14 changes: 7 additions & 7 deletions llvm/test/TableGen/DecoderEmitter/operand-decoder.td
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Expand Up @@ -17,25 +17,25 @@ def MyTarget : Target {
// CHECK-NEXT: tmp = fieldFromInstruction(insn, 2, 4);
// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
// CHECK-NEXT: tmp = 0x0;
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 0, 2), 0, 2);
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 6, 2), 2, 2);
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 0, 2);
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 6, 2) << 2;
// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
// CHECK-NEXT: tmp = 0x0;
// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
// CHECK-NEXT: tmp = fieldFromInstruction(insn, 13, 2) << 1;
// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
// CHECK-NEXT: tmp = 0x0;
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 17, 1), 1, 1);
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 19, 1), 3, 1);
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 17, 1) << 1;
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 19, 1) << 3;
// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
// CHECK-NEXT: tmp = 0x5;
// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
// CHECK-NEXT: tmp = 0x2;
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 26, 2), 2, 2);
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 26, 2) << 2;
// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
// CHECK-NEXT: tmp = 0xa;
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 28, 1), 0, 1);
// CHECK-NEXT: insertBits(tmp, fieldFromInstruction(insn, 30, 1), 2, 1);
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 28, 1);
// CHECK-NEXT: tmp |= fieldFromInstruction(insn, 30, 1) << 2;
// CHECK-NEXT: MI.addOperand(MCOperand::createImm(tmp));
// CHECK-NEXT: return S;

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10 changes: 7 additions & 3 deletions llvm/utils/TableGen/DecoderEmitter.cpp
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Expand Up @@ -1041,9 +1041,13 @@ static void emitBinaryParser(raw_ostream &OS, indent Indent,
// insert the variable parts into it.
OS << Indent << "tmp = " << format_hex(OpInfo.InitValue.value_or(0), 0)
<< ";\n";
for (auto [Base, Width, Offset] : OpInfo.fields())
OS << Indent << "insertBits(tmp, fieldFromInstruction(insn, " << Base
<< ", " << Width << "), " << Offset << ", " << Width << ");\n";
for (auto [Base, Width, Offset] : OpInfo.fields()) {
OS << Indent << "tmp |= fieldFromInstruction(insn, " << Base << ", "
<< Width << ')';
if (Offset)
OS << " << " << Offset;
OS << ";\n";
}
}

StringRef Decoder = OpInfo.Decoder;
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