AMDGPU: Constrain regclass when replacing SGPRs with VGPRs

[arsenm]

We need to account for local instruction constraints after
finding a replacement VGPR class. This solves expensive_checks
failures in existing tests.

[arsenm]

• AMDGPU: Remove unnecessary operand legalization for WMMAs #159370
• AMDGPU: Constrain regclass when replacing SGPRs with VGPRs #159369 👈 (View in Graphite)
• main

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[llvmbot]

@llvm/pr-subscribers-backend-amdgpu

Author: Matt Arsenault (arsenm)

Changes

We need to account for local instruction constraints after
finding a replacement VGPR class. This solves expensive_checks
failures in existing tests.

---

Full diff: https://github.com/llvm/llvm-project/pull/159369.diff

1 Files Affected:

• (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+4-1)

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index c39da779ecf8c..37c75fe7f7dfd 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8993,7 +8993,10 @@ void SIInstrInfo::addUsersToMoveToVALUWorklist(
       break;
     }
 
-    if (!RI.hasVectorRegisters(getOpRegClass(UseMI, OpNo)))
+    const TargetRegisterClass *OpRC = getOpRegClass(UseMI, OpNo);
+    MRI.constrainRegClass(DstReg, OpRC);
+
+    if (!RI.hasVectorRegisters(OpRC))
       Worklist.insert(&UseMI);
     else
       // Legalization could change user list.